From: "Chautru, Nicolas" <nicolas.chautru@intel.com>
To: Maxime Coquelin <maxime.coquelin@redhat.com>,
"dev@dpdk.org" <dev@dpdk.org>,
"gakhil@marvell.com" <gakhil@marvell.com>,
"trix@redhat.com" <trix@redhat.com>
Cc: "thomas@monjalon.net" <thomas@monjalon.net>,
"Kinsella, Ray" <ray.kinsella@intel.com>,
"Richardson, Bruce" <bruce.richardson@intel.com>,
"hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
"Vargas, Hernan" <hernan.vargas@intel.com>,
"david.marchand@redhat.com" <david.marchand@redhat.com>
Subject: RE: [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF
Date: Tue, 31 May 2022 18:28:10 +0000 [thread overview]
Message-ID: <BY5PR11MB4451C635F329638FD4BFE6E5F8DC9@BY5PR11MB4451.namprd11.prod.outlook.com> (raw)
In-Reply-To: <b796748d-7a98-0dee-7b55-3af29202aea4@redhat.com>
Hi Maxime,
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Tuesday, May 31, 2022 12:36 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from
> PF
>
> Hi Nicolas,
>
> Thanks for doing the API change, this part looks good to me now.
> I just have one comment below that was not addressed:
>
> On 5/26/22 02:55, Nicolas Chautru wrote:
> > Adding companion function common to ACC100/ACC101 which can be
> called
> > from bbdev-test when running from PF.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > app/test-bbdev/test_bbdev_perf.c | 6 +-
> > drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> > drivers/baseband/acc100/rte_acc100_pmd.c | 323
> ++++++++++++++++++++++++++++++-
> > drivers/baseband/acc100/version.map | 3 +-
> > 4 files changed, 327 insertions(+), 9 deletions(-)
> >
>
> ...
>
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index a057edf..86545cc 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -4574,8 +4574,8 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > }
> >
> > /* Initial configuration of a ACC100 device prior to running
> > configure() */ -int -rte_acc100_configure(const char *dev_name, struct
> > rte_acc100_conf *conf)
> > +static int
> > +acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
> > {
> > rte_bbdev_log(INFO, "rte_acc100_configure");
> > uint32_t value, address, status;
> > @@ -4975,3 +4975,322 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > rte_bbdev_log_debug("PF Tip configuration complete for %s",
> dev_name);
> > return 0;
> > }
> > +
> > +
> > +/* Initial configuration of a ACC101 device prior to running
> > +configure() */ static int acc101_configure(const char *dev_name,
> > +struct rte_acc100_conf *conf) {
> > + rte_bbdev_log(INFO, "rte_acc101_configure");
> > + uint32_t value, address, status;
> > + int qg_idx, template_idx, vf_idx, acc, i;
> > + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> > +
> > + /* Compile time checks */
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
> > +
> > + if (bbdev == NULL) {
> > + rte_bbdev_log(ERR,
> > + "Invalid dev_name (%s), or device is not yet initialised",
> > + dev_name);
> > + return -ENODEV;
> > + }
> > + struct acc100_device *d = bbdev->data->dev_private;
> > +
> > + /* Store configuration */
> > + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
> > +
> > + /* PCIe Bridge configuration */
> > + acc100_reg_write(d, HwPfPcieGpexBridgeControl,
> ACC101_CFG_PCI_BRIDGE);
> > + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
> > + acc100_reg_write(d,
> HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i
> > +* 16, 0);
> > +
> > + /* Prevent blocking AXI read on BRESP for AXI Write */
> > + address = HwPfPcieGpexAxiPioControl;
> > + value = ACC101_CFG_PCI_AXI;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Explicitly releasing AXI including a 2ms delay on ACC101 */
> > + usleep(2000);
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* Set the default 5GDL DMA configuration */
> > + acc100_reg_write(d, HWPfDmaInboundDrainDataSize,
> > +ACC101_DMA_INBOUND);
> > +
> > + /* Enable granular dynamic clock gating */
> > + address = HWPfHiClkGateHystReg;
> > + value = ACC101_CLOCK_GATING_EN;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Set default descriptor signature */
> > + address = HWPfDmaDescriptorSignatuture;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Enable the Error Detection in DMA */
> > + value = ACC101_CFG_DMA_ERROR;
> > + address = HWPfDmaErrorDetectionEn;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* AXI Cache configuration */
> > + value = ACC101_CFG_AXI_CACHE;
> > + address = HWPfDmaAxcacheReg;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default DMA Configuration (Qmgr Enabled) */
> > + address = HWPfDmaConfig0Reg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfDmaQmanen;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default RLIM/ALEN configuration */
> > + address = HWPfDmaConfig1Reg;
> > + int alen_r = 0xF;
> > + int alen_w = 0x7;
> > + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configure DMA Qmanager addresses */
> > + address = HWPfDmaQmgrAddrReg;
> > + value = HWPfQmgrEgressQueuesTemplate;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* ===== Qmgr Configuration ===== */
> > + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2
> for UL */
> > + int totalQgs = conf->q_ul_4g.num_qgroups +
> > + conf->q_ul_5g.num_qgroups +
> > + conf->q_dl_4g.num_qgroups +
> > + conf->q_dl_5g.num_qgroups;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrDepthLog2Grp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = aqDepth(qg_idx, conf);
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrTholdGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Template Priority in incremental order */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg0Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg1Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_1;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg2indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_2;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg3Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_3;
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + address = HWPfQmgrGrpPriority;
> > + value = ACC101_CFG_QMGR_HI_P;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Template Configuration */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + value = 0;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 4GUL */
> > + int numQgs = conf->q_ul_4g.num_qgroups;
> > + int numQqsAcc = 0;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_4G;
> > + template_idx <= ACC101_SIG_UL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 5GUL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_ul_5g.num_qgroups;
> > + value = 0;
> > + int numEngines = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_5G;
> > + template_idx <= ACC101_SIG_UL_5G_LAST;
> > + template_idx++) {
> > + /* Check engine power-on status */
> > + address = HwPfFecUl5gIbDebugReg +
> > + ACC101_ENGINE_OFFSET * template_idx;
> > + status = (acc100_reg_read(d, address) >> 4) & 0xF;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + if (status == 1) {
> > + acc100_reg_write(d, address, value);
> > + numEngines++;
> > + } else
> > + acc100_reg_write(d, address, 0);
> > +#if RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > + printf("Number of 5GUL engines %d\n", numEngines);
> > + /* 4GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_4g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_4G;
> > + template_idx <= ACC101_SIG_DL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value); #if
> RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
>
> As I mentionned on previous revision, single FEC case should be handled via
> a devarg, so that testing both cases do not require a rebuild.
This is already done like this in ACC100 and is meant to be a build time parameter.
Still I will take it out of the commit to avoid any confusion.
Thanks
>
> > + }
> > + /* 5GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_5g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_5G;
> > + template_idx <= ACC101_SIG_DL_5G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value); #if
> RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > +
> > + /* Queue Group Function mapping */
> > + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> > + address = HWPfQmgrGrpFunction0;
> > + value = 0;
> > + for (qg_idx = 0; qg_idx < 8; qg_idx++) {
> > + acc = accFromQgid(qg_idx, conf);
> > + value |= qman_func_id[acc]<<(qg_idx * 4);
> > + }
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configuration of the Arbitration QGroup depth to 1 */
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrArbQDepthGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Enabling AQueues through the Queue hierarchy*/
> > + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
> > + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
> > + value = 0;
> > + if (vf_idx < conf->num_vf_bundles &&
> > + qg_idx < totalQgs)
> > + value = (1 << aqNum(qg_idx, conf)) - 1;
> > + address = HWPfQmgrAqEnableVf
> > + + vf_idx * ACC101_BYTES_IN_WORD;
> > + value += (qg_idx << 16);
> > + acc100_reg_write(d, address, value);
> > + }
> > + }
> > +
> > + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
> > + uint32_t aram_address = 0;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfQmgrVfBaseAddr + vf_idx
> > + * ACC101_BYTES_IN_WORD + qg_idx
> > + * ACC101_BYTES_IN_WORD * 64;
> > + value = aram_address;
> > + acc100_reg_write(d, address, value);
> > + /* Offset ARAM Address for next memory bank
> > + * - increment of 4B
> > + */
> > + aram_address += aqNum(qg_idx, conf) *
> > + (1 << aqDepth(qg_idx, conf));
> > + }
> > + }
> > +
> > + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
> > + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d
> %d\n",
> > + aram_address,
> ACC101_WORDS_IN_ARAM_SIZE);
> > + return -EINVAL;
> > + }
> > +
> > + /* ==== HI Configuration ==== */
> > +
> > + /* No Info Ring/MSI by default */
> > + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
> > + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
> > + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
> > + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
> > + /* Prevent Block on Transmit Error */
> > + address = HWPfHiBlockTransmitOnErrorEn;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Prevents to drop MSI */
> > + address = HWPfHiMsiDropEnableReg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Set the PF Mode register */
> > + address = HWPfHiPfMode;
> > + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
> > + acc100_reg_write(d, address, value);
> > + /* Explicitly releasing AXI after PF Mode and 2 ms */
> > + usleep(2000);
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* QoS overflow init */
> > + value = 1;
> > + address = HWPfQosmonAEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQosmonBEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* HARQ DDR Configuration */
> > + unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfDmaVfDdrBaseRw + vf_idx
> > + * 0x10;
> > + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
> > + (ddrSizeInMb - 1);
> > + acc100_reg_write(d, address, value);
> > + }
> > + usleep(ACC101_LONG_WAIT);
> > +
> > + rte_bbdev_log_debug("PF TIP configuration complete for %s",
> dev_name);
> > + return 0;
> > +}
> > +
> > +int
> > +rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf
> > +*conf) {
> > + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> > + if (bbdev == NULL) {
> > + rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not
> yet initialised",
> > + dev_name);
> > + return -ENODEV;
> > + }
> > + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
> > + printf("Configure dev id %x\n", pci_dev->id.device_id);
> > + if (pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID)
> > + return acc100_configure(dev_name, conf);
> > + else
> > + return acc101_configure(dev_name, conf); }
next prev parent reply other threads:[~2022-05-31 18:28 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-04-27 18:16 ` [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-08 13:02 ` Tom Rix
2022-05-09 21:23 ` Chautru, Nicolas
2022-05-10 8:52 ` Thomas Monjalon
2022-05-10 11:55 ` Tom Rix
2022-05-23 17:53 ` Chautru, Nicolas
2022-04-27 18:17 ` [PATCH v2 2/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-08 13:07 ` Tom Rix
2022-05-09 21:27 ` Chautru, Nicolas
2022-04-27 18:17 ` [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-08 13:38 ` Tom Rix
2022-05-09 21:36 ` Chautru, Nicolas
2022-05-10 12:02 ` Tom Rix
2022-04-27 18:17 ` [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD Nicolas Chautru
2022-05-08 13:44 ` Tom Rix
2022-05-09 22:07 ` Chautru, Nicolas
2022-04-27 18:17 ` [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-08 13:55 ` Tom Rix
2022-05-09 21:45 ` Chautru, Nicolas
2022-05-10 12:11 ` Tom Rix
2022-05-10 14:44 ` Thomas Monjalon
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-19 19:55 ` Maxime Coquelin
2022-05-16 20:48 ` [PATCH v3 2/4] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-19 20:13 ` Maxime Coquelin
2022-05-23 17:06 ` Chautru, Nicolas
2022-05-16 20:48 ` [PATCH v3 4/4] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-19 19:51 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Tom Rix
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-25 14:33 ` Maxime Coquelin
2022-05-25 22:15 ` Chautru, Nicolas
2022-05-31 7:59 ` Maxime Coquelin
2022-05-31 18:19 ` Chautru, Nicolas
2022-05-24 0:08 ` [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-25 13:24 ` Maxime Coquelin
2022-05-25 22:09 ` Chautru, Nicolas
2022-05-26 0:49 ` [PATCH v6 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-26 0:55 ` Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-30 7:40 ` [EXT] " Akhil Goyal
2022-05-31 18:59 ` Chautru, Nicolas
2022-05-26 0:55 ` [PATCH v6 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-31 8:02 ` Maxime Coquelin
2022-05-31 18:16 ` Chautru, Nicolas
2022-05-26 0:55 ` [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-31 7:35 ` Maxime Coquelin
2022-05-31 18:28 ` Chautru, Nicolas [this message]
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-31 22:31 ` [PATCH v7 1/6] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-06-02 9:49 ` Kevin Traynor
2022-06-02 16:52 ` Chautru, Nicolas
2022-06-03 20:25 ` Vargas, Hernan
2022-05-31 22:31 ` [PATCH v7 2/6] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-06-02 8:21 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro Nicolas Chautru
2022-06-01 14:11 ` Maxime Coquelin
2022-06-01 17:15 ` [EXT] " Akhil Goyal
2022-06-02 12:57 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 4/6] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-06-02 12:23 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 5/6] baseband/acc100: modify validation code " Nicolas Chautru
2022-06-03 20:23 ` Vargas, Hernan
2022-05-31 22:31 ` [PATCH v7 6/6] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-06-02 8:33 ` Maxime Coquelin
2022-06-06 14:54 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Chautru, Nicolas
2022-06-06 15:03 ` Akhil Goyal
2022-06-06 16:18 ` Chautru, Nicolas
2022-06-15 14:08 ` [EXT] " Akhil Goyal
2022-06-22 11:50 ` Akhil Goyal
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