From: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
To: David Christensen <drc@linux.vnet.ibm.com>,
Jerin Jacob Kollanukkaran <jerinj@marvell.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, "stable@dpdk.org" <stable@dpdk.org>
Subject: RE: [EXT] Re: [PATCH v2 1/5] examples/l3fwd: fix port group mask generation
Date: Fri, 9 Sep 2022 05:56:53 +0000 [thread overview]
Message-ID: <CO6PR18MB40841DE0BE1485D67FF818ABDE439@CO6PR18MB4084.namprd18.prod.outlook.com> (raw)
In-Reply-To: <d8dc9469-c222-847c-82c5-f0af659d9495@linux.vnet.ibm.com>
> On 9/2/22 2:18 AM, pbhagavatula@marvell.com wrote:
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> >
> > Fix port group mask generation in altivec, vec_any_eq returns
> > 0 or 1 while port_groupx4 expects comparison mask result.
> >
> > Fixes: 2193b7467f7a ("examples/l3fwd: optimize packet processing on
> powerpc")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > ---
> > v2 Changes:
> > - Fix PPC, RISC-V, aarch32 compilation.
> >
> > examples/common/altivec/port_group.h | 11 +++++++++--
> > 1 file changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/examples/common/altivec/port_group.h
> b/examples/common/altivec/port_group.h
> > index 5e209b02fa..592ef80b7f 100644
> > --- a/examples/common/altivec/port_group.h
> > +++ b/examples/common/altivec/port_group.h
> > @@ -26,12 +26,19 @@ port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t
> *lp,
> > uint16_t u16[FWDSTEP + 1];
> > uint64_t u64;
> > } *pnum = (void *)pn;
> > + union u_vec {
> > + __vector unsigned short v_us;
> > + unsigned short s[8];
> > + };
> >
> > + union u_vec res;
> > int32_t v;
> >
> > - v = vec_any_eq(dp1, dp2);
> > -
> > + dp1 = (__vector unsigned short)vec_cmpeq(dp1, dp2);
>
> Altivec vec_cmpeq() is similar to Intel _mm_cmpeq_*(), so this looks
> right to me.
>
> > + res.v_us = dp1;
> >
> > + v = (res.s[0] & 0x1) | (res.s[1] & 0x2) | (res.s[2] & 0x4) |
> > + (res.s[3] & 0x8);
>
> This can be vectorized too. The Intel _mm_unpacklo_epi16() intrinsic
> can be replaced with the following Altivec code:
>
> extern __inline __m128i __attribute__((__gnu_inline__,
> __always_inline__, __artificial__))
> _mm_unpacklo_epi16 (__m128i __A, __m128i __B)
> {
> return (__m128i) vec_mergeh ((__v8hi)__A, (__v8hi)__B);
> }
>
> The Intel _mm_movemask_ps() intrinsic can be replaced with the following
> Altivec implementation:
>
> /* Creates a 4-bit mask from the most significant bits of the SPFP
> values. */
> extern __inline int __attribute__((__gnu_inline__, __always_inline__,
> __artificial__))
> _mm_movemask_ps (__m128 __A)
> {
> __vector unsigned long long result;
> static const __vector unsigned int perm_mask =
> {
> #ifdef __LITTLE_ENDIAN__
> 0x00204060, 0x80808080, 0x80808080, 0x80808080
> #else
> 0x80808080, 0x80808080, 0x80808080, 0x00204060
> #endif
> };
>
> result = ((__vector unsigned long long)
> vec_vbpermq ((__vector unsigned char) __A,
> (__vector unsigned char) perm_mask));
>
> #ifdef __LITTLE_ENDIAN__
> return result[1];
> #else
> return result[0];
> #endif
> }
>
Sure I will add this to the next version.
> Dave
Thanks,
Pavan.
next prev parent reply other threads:[~2022-09-09 5:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-29 9:44 [PATCH " pbhagavatula
2022-09-02 9:18 ` [PATCH v2 " pbhagavatula
2022-09-08 18:33 ` David Christensen
2022-09-09 5:56 ` Pavan Nikhilesh Bhagavatula [this message]
2022-09-11 18:12 ` [PATCH v3 " pbhagavatula
2022-10-11 9:08 ` [PATCH v4 " pbhagavatula
2022-10-11 10:12 ` [PATCH v5 " pbhagavatula
2022-10-17 12:05 ` [EXT] " Shijith Thotton
2022-10-20 16:15 ` Pavan Nikhilesh Bhagavatula
2022-10-25 16:05 ` [PATCH v6 " pbhagavatula
2022-10-31 14:52 ` Thomas Monjalon
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