From: "Zhang, Qi Z" <qi.z.zhang@intel.com>
To: Simon Ellmann <simon.ellmann@tum.de>
Cc: "Yang, Qiming" <qiming.yang@intel.com>,
"Wu, Wenjun1" <wenjun1.wu@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>
Subject: RE: [PATCH] ixgbe: fix interrupt clear mask for eimc register
Date: Tue, 19 Dec 2023 03:32:28 +0000 [thread overview]
Message-ID: <DM4PR11MB5994F56381F9144E0E73CBACD797A@DM4PR11MB5994.namprd11.prod.outlook.com> (raw)
In-Reply-To: <11D28166-82CE-4E28-A04F-4C14EF9EF5C9@tum.de>
> -----Original Message-----
> From: Simon Ellmann <simon.ellmann@tum.de>
> Sent: Thursday, December 14, 2023 7:03 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: Yang, Qiming <qiming.yang@intel.com>; Wu, Wenjun1
> <wenjun1.wu@intel.com>; dev@dpdk.org
> Subject: Re: [PATCH] ixgbe: fix interrupt clear mask for eimc register
>
> > On 14. Dec 2023, at 03:24, Zhang, Qi Z <qi.z.zhang@intel.com> wrote:
> >> -----Original Message-----
> >> From: Simon Ellmann <simon.ellmann@tum.de>
> >> Sent: Friday, December 8, 2023 11:44 PM
> >> To: Yang, Qiming <qiming.yang@intel.com>; Wu, Wenjun1
> >> <wenjun1.wu@intel.com>
> >> Cc: dev@dpdk.org; Simon Ellmann <simon.ellmann@tum.de>
> >> Subject: [PATCH] ixgbe: fix interrupt clear mask for eimc register
> >>
> >> 32nd bit of the eimc register is reserved according to the datasheet
> >>
> >> Signed-off-by: Simon Ellmann <simon.ellmann@tum.de>
> >> ---
> >> drivers/net/ixgbe/base/ixgbe_type.h | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
> >> b/drivers/net/ixgbe/base/ixgbe_type.h
> >> index 1094df5891..03b299cd10 100644
> >> --- a/drivers/net/ixgbe/base/ixgbe_type.h
> >> +++ b/drivers/net/ixgbe/base/ixgbe_type.h
> >> @@ -2023,7 +2023,7 @@ enum {
> >> #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
> >>
> >> /* Interrupt clear mask */
> >> -#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
> >> +#define IXGBE_IRQ_CLEAR_MASK 0x7FFFFFFF
> >
> > If it is not harmful, I will prefer to keep the base code aligned with kernel
> driver's implementation which is 0xFFFFFFFF currently.
>
> Alright. We fixed this in our driver implementation –
> https://github.com/ixy-languages/ixy.rs/issues/29 – and thought we would
> let you know.
Thanks
>
> >>
> >> /* Interrupt Vector Allocation Registers */
> >> #define IXGBE_IVAR_REG_NUM 25
> >> --
> >> 2.43.0
> >
prev parent reply other threads:[~2023-12-19 3:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-08 15:44 Simon Ellmann
2023-12-14 2:24 ` Zhang, Qi Z
2023-12-14 11:02 ` Simon Ellmann
2023-12-19 3:32 ` Zhang, Qi Z [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=DM4PR11MB5994F56381F9144E0E73CBACD797A@DM4PR11MB5994.namprd11.prod.outlook.com \
--to=qi.z.zhang@intel.com \
--cc=dev@dpdk.org \
--cc=qiming.yang@intel.com \
--cc=simon.ellmann@tum.de \
--cc=wenjun1.wu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).