From: Ori Kam <orika@nvidia.com>
To: NBU-Contact-Thomas Monjalon <thomas@monjalon.net>
Cc: Slava Ovsiienko <viacheslavo@nvidia.com>,
"ferruh.yigit@intel.com" <ferruh.yigit@intel.com>,
Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,
"dev@dpdk.org" <dev@dpdk.org>,
"ajit.khaparde@broadcom.com" <ajit.khaparde@broadcom.com>,
"jerinj@marvell.com" <jerinj@marvell.com>
Subject: Re: [dpdk-dev] [RFC] ethdev: add sanity packet checks
Date: Thu, 4 Mar 2021 10:00:38 +0000 [thread overview]
Message-ID: <DM6PR12MB4987F6384627FDEF6800F76ED6979@DM6PR12MB4987.namprd12.prod.outlook.com> (raw)
In-Reply-To: <1769565.OWqOAu9aEJ@thomas>
Hi
PSB
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Thomas Monjalon
> Sent: Sunday, February 28, 2021 10:14 PM
>
> 28/02/2021 20:48, Ori Kam:
> > Currently, DPDK application can offload the checksum check,
> > and report it in the mbuf.
> >
> > However, this approach doesn't work if the traffic
> > is offloaded and should not arrive to the application.
> >
> > This commit introduces rte flow item that enables
>
> s/rte flow/rte_flow/
>
Sure
> > matching on the checksum of the L3 and L4 layers,
> > in addition to other checks that can determine if
> > the packet is valid.
> > some of those tests can be packet len, data len,
> > unsupported flags, and so on.
> >
> > The full check is HW dependent.
>
> What is the "full check"?
> How much it is HW dependent?
>
This also relates to your other comments,
Each HW may run different set of checks on the packet,
for example one PMD can just check the tcp flags while
a different PMD will also check the option.
>
> > + * RTE_FLOW_ITEM_TYPE_SANITY_CHECKS
> > + *
> > + * Enable matching on packet validity based on HW checks for the L3 and L4
> > + * layers.
> > + */
> > +struct rte_flow_item_sanity_checks {
> > + uint32_t level;
> > + /**< Packet encapsulation level the item should apply to.
> > + * @see rte_flow_action_rss
> > + */
> > +RTE_STD_C11
> > + union {
> > + struct {
>
> Why there is no L2 check?
>
Our HW doesn't support it.
If other HW support it, it should be added.
> > + uint32_t l3_ok:1;
> > + /**< L3 layer is valid after passing all HW checking. */
> > + uint32_t l4_ok:1;
> > + /**< L4 layer is valid after passing all HW checking. */
>
> l3_ok and l4_ok looks vague.
> What does it cover exactly?
>
It depends on the HW in question.
In our case it checks in case of L3
the header len, and the version.
For L4 checking the len.
> > + uint32_t l3_ok_csum:1;
> > + /**< L3 layer checksum is valid. */
> > + uint32_t l4_ok_csum:1;
> > + /**< L4 layer checksum is valid. */
> > + uint32_t reserved:28;
> > + };
> > + uint32_t value;
> > + };
> > +};
>
>
Best,
Ori
next prev parent reply other threads:[~2021-03-04 10:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-28 19:48 Ori Kam
2021-02-28 20:14 ` Thomas Monjalon
2021-03-04 10:00 ` Ori Kam [this message]
2021-03-04 10:46 ` Thomas Monjalon
2021-03-07 18:46 ` Ori Kam
2021-03-08 23:05 ` Ajit Khaparde
2021-03-09 19:21 ` Ori Kam
2021-03-09 9:01 ` Andrew Rybchenko
2021-03-09 9:11 ` Thomas Monjalon
2021-03-09 15:08 ` Ori Kam
2021-03-09 15:27 ` Andrew Rybchenko
2021-03-09 19:46 ` Ori Kam
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