From: "Zhang, Helin" <helin.zhang@intel.com>
To: "xuelin.shi@freescale.com" <xuelin.shi@freescale.com>,
"thomas.monjalon@6wind.com" <thomas.monjalon@6wind.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe PCI and CPU
Date: Mon, 15 Jun 2015 00:52:44 +0000 [thread overview]
Message-ID: <F35DEAC7BCE34641BA9FAC6BCA4A12E70A881C81@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <1423637385-25077-1-git-send-email-xuelin.shi@freescale.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of
> xuelin.shi@freescale.com
> Sent: Wednesday, February 11, 2015 2:50 PM
> To: thomas.monjalon@6wind.com
> Cc: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe
> PCI and CPU
>
> From: Xuelin Shi <xuelin.shi@freescale.com>
>
> make sure:
> CPU read from ixgbe with IXGBE_LE32_TO_CPUS
> CPU write to ixgbe with IXGBE_CPU_TO_LE32
>
> otherwise, there is endian issue for ixgbe on BIG_ENDIAN CPU.
>
> Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com>
NACK, see my comments @ http://www.dpdk.org/ml/archives/dev/2015-March/015640.html
> ---
> .../linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h | 24
> ++++++++++++++++------
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> index d161600..0612632 100644
> --- a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> +++ b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> @@ -53,6 +53,16 @@
>
> #undef ASSERT
>
> +static inline uint32_t ixgbe_read_addr(volatile void* addr) {
> + return IXGBE_LE32_TO_CPUS(*((volatile uint32_t *)addr)); }
> +
> +static inline uint32_t ixgbe_write_addr(u32 value, volatile void* addr)
> +{
> + return writel(IXGBE_CPU_TO_LE32(value), addr); }
> +
> #ifdef DBG
> #define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A)
> #else
> @@ -91,19 +101,20 @@
> default: \
> break; \
> } \
> - writel((value), ((a)->hw_addr + (reg))); \
> + ixgbe_write_addr((value), ((a)->hw_addr + (reg))); \
> } while (0)
> #else
> -#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
> +#define IXGBE_WRITE_REG(a, reg, value) \
> + ixgbe_write_addr((value), ((a)->hw_addr + (reg)))
> #endif
>
> -#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
> +#define IXGBE_READ_REG(a, reg) ixgbe_read_addr((a)->hw_addr + (reg))
>
> #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
> - writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
> + ixgbe_write_addr((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
>
> #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
> - readl((a)->hw_addr + (reg) + ((offset) << 2)))
> + ixgbe_read_addr((a)->hw_addr + (reg) + ((offset) << 2)))
>
> #ifndef writeq
> #define writeq(val, addr) do { writel((u32) (val), addr); \
> @@ -111,7 +122,8 @@
> } while (0);
> #endif
>
> -#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr +
> (reg)))
> +#define IXGBE_WRITE_REG64(a, reg, value) \
> + writeq((cpu_to_le64(value)), ((a)->hw_addr + (reg)))
>
> #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) struct
> ixgbe_hw;
> --
> 1.9.1
prev parent reply other threads:[~2015-06-15 0:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-11 6:49 xuelin.shi
2015-02-20 10:55 ` Thomas Monjalon
2015-03-23 13:58 ` Thomas Monjalon
2015-03-24 1:54 ` Zhang, Helin
2015-06-15 0:52 ` Zhang, Helin [this message]
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