From: Raslan Darawsheh <rasland@nvidia.com>
To: Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>,
Slava Ovsiienko <viacheslavo@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: RE: [PATCH] net/mlx5: fix GENEVE resource management
Date: Thu, 17 Nov 2022 08:38:05 +0000 [thread overview]
Message-ID: <MN2PR12MB3086ED516D1A3D92FC8B3173CF069@MN2PR12MB3086.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20221116093654.19165-1-suanmingm@nvidia.com>
Hi,
> -----Original Message-----
> From: Suanming Mou <suanmingm@nvidia.com>
> Sent: Wednesday, November 16, 2022 11:37 AM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>
> Subject: [PATCH] net/mlx5: fix GENEVE resource management
>
> The item translation split causes GENEVE TLV option resource register
> function flow_dev_geneve_tlv_option_resource_register() to be called
> twice incorrectly both in spec and mask translation.
>
> In SWS mode the refcnt will only be decreased by 1 in flow release.
> The refcnt will never be 0 again, it causes the resource be leaked.
> In HWS mode the resource is allocated as global, the refcnt should
> not be increased after the resource be allocated. And the resource
> should be released during PMD exists.
>
> This commit fixes GENEVE resource management.
>
> Fixes: 75a00812b18f ("net/mlx5: add hardware steering item translation")
> Fixes: cd4ab742064a ("net/mlx5: split flow item matcher and value
> translation")
>
> Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
prev parent reply other threads:[~2022-11-17 8:38 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-16 9:36 Suanming Mou
2022-11-17 8:38 ` Raslan Darawsheh [this message]
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