From: Akhil Goyal <gakhil@marvell.com>
To: Rahul Bhansali <rbhansali@marvell.com>,
"dev@dpdk.org" <dev@dpdk.org>,
Radu Nicolau <radu.nicolau@intel.com>
Cc: "hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
Gagandeep Singh <g.singh@nxp.com>
Subject: RE: [PATCH] examples/ipsec-secgw: support for per SA HW reassembly
Date: Fri, 21 Oct 2022 15:57:32 +0000 [thread overview]
Message-ID: <PH0PR18MB449176AA6667DF22E5BC8D23D82D9@PH0PR18MB4491.namprd18.prod.outlook.com> (raw)
In-Reply-To: <20220829151233.2515424-1-rbhansali@marvell.com>
> @@ -142,7 +144,7 @@ extern volatile bool force_quit;
> extern uint32_t nb_bufs_in_pool;
>
> extern bool per_port_pool;
> -
> +extern int ip_reassembly_dynfield_offset;
> extern uint32_t mtu_size;
> extern uint32_t frag_tbl_sz;
>
> @@ -186,6 +188,46 @@ core_stats_update_drop(int n)
> core_statistics[lcore_id].dropped += n;
> }
>
> +static inline void
> +core_stats_update_frag_drop(int n)
> +{
> + int lcore_id = rte_lcore_id();
> + core_statistics[lcore_id].frag_dropped += n;
> +}
> +
> +extern uint64_t ip_reassembly_dynflag;
A nit, move this extern next to ip_reassembly_dynfield_offset
Apart from that
Acked-by: Akhil Goyal <gakhil@marvell.com>
Also change the patch title as
examples/ipsec-secgw: support per SA HW reassembly
next prev parent reply other threads:[~2022-10-21 15:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-29 15:12 Rahul Bhansali
2022-10-21 15:57 ` Akhil Goyal [this message]
2022-10-27 11:05 ` [PATCH v2] examples/ipsec-secgw: support " Rahul Bhansali
2022-10-27 14:13 ` Akhil Goyal
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