From: "Ji, Kai" <kai.ji@intel.com>
To: "Kusztal, ArkadiuszX" <arkadiuszx.kusztal@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: "gakhil@marvell.com" <gakhil@marvell.com>
Subject: RE: [PATCH v2] common/qat: read hw slice configuration
Date: Sun, 16 Oct 2022 22:24:31 +0000 [thread overview]
Message-ID: <SN6PR11MB3408D2D20F9DC51814F8DB6981269@SN6PR11MB3408.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20221013140233.82512-1-arkadiuszx.kusztal@intel.com>
> -----Original Message-----
> From: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>
> Sent: Thursday, October 13, 2022 3:03 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Ji, Kai <kai.ji@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH v2] common/qat: read hw slice configuration
>
> Read slice configuration of QAT capabilities.
> This will allow to recognize if specific hw function is available on particular
> device.
>
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
[KJ] any documentation update needed for qat.rst ?
> ---
> drivers/common/qat/dev/qat_dev_gen1.c | 8 +++
> drivers/common/qat/dev/qat_dev_gen2.c | 8 +++
> drivers/common/qat/dev/qat_dev_gen3.c | 14 +++++
> drivers/common/qat/dev/qat_dev_gen4.c | 8 +++
> drivers/common/qat/qat_adf/icp_qat_hw.h | 18 +++++++
> drivers/common/qat/qat_device.c | 10 +++-
> drivers/common/qat/qat_device.h | 5 ++
> drivers/crypto/qat/dev/qat_asym_pmd_gen1.c | 42 ++++++++++++---
> drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 41 +++++++++++---
> drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 80
> +++++++++++++++++++++++++---
> drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 41 +++++++++++---
> drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 5 +-
> drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 41 +++++++++++---
> drivers/crypto/qat/qat_asym.c | 49 ++++++++---------
> drivers/crypto/qat/qat_crypto.h | 4 +-
> drivers/crypto/qat/qat_sym.c | 38 +++++--------
> 16 files changed, 324 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/common/qat/dev/qat_dev_gen1.c
> b/drivers/common/qat/dev/qat_dev_gen1.c
> index c34ae5a51c..0be5b9077c 100644
> --- a/drivers/common/qat/dev/qat_dev_gen1.c
> +++ b/drivers/common/qat/dev/qat_dev_gen1.c
> @@ -241,12 +241,20 @@ qat_dev_get_extra_size_gen1(void)
> return 0;
> }
>
> +static int
> +qat_get_slice_map_gen1(uint16_t *map __rte_unused,
> + const struct rte_pci_device *pci_dev __rte_unused) {
> + return 0;
> +}
> +
> static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen1 = {
> .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
> .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
> .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
> .qat_dev_read_config = qat_dev_read_config_gen1,
> .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
> + .qat_get_slice_map = qat_get_slice_map_gen1,
[KJ] qat_dev_get_slice_map ?
> };
>
> RTE_INIT(qat_dev_gen_gen1_init)
> diff --git a/drivers/common/qat/dev/qat_dev_gen2.c
> b/drivers/common/qat/dev/qat_dev_gen2.c
> index f077fe9eef..cb60fe5309 100644
> --- a/drivers/common/qat/dev/qat_dev_gen2.c
> +++ b/drivers/common/qat/dev/qat_dev_gen2.c
> @@ -21,12 +21,20 @@ static struct qat_qp_hw_spec_funcs
> qat_qp_hw_spec_gen2 = {
> .qat_qp_get_hw_data = qat_qp_get_hw_data_gen1, };
>
> +static int
> +qat_get_slice_map_gen2(uint16_t *map __rte_unused,
> + const struct rte_pci_device *pci_dev __rte_unused) {
> + return 0;
> +}
> +
> static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen2 = {
> .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
> .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
> .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
> .qat_dev_read_config = qat_dev_read_config_gen1,
> .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
> + .qat_get_slice_map = qat_get_slice_map_gen2,
> };
>
> RTE_INIT(qat_dev_gen_gen2_init)
> diff --git a/drivers/common/qat/dev/qat_dev_gen3.c
> b/drivers/common/qat/dev/qat_dev_gen3.c
> index de3fa17fa9..681c946ede 100644
> --- a/drivers/common/qat/dev/qat_dev_gen3.c
> +++ b/drivers/common/qat/dev/qat_dev_gen3.c
> @@ -5,6 +5,7 @@
> #include "qat_device.h"
> #include "qat_qp.h"
> #include "adf_transport_access_macros.h"
> +#include "icp_qat_hw.h"
[KJ] consider move this header file in qat_device.h
> #include "qat_dev_gens.h"
>
<snip>
> diff --git a/drivers/common/qat/qat_device.h
> b/drivers/common/qat/qat_device.h index d1512f3b89..175b801a6c 100644
> --- a/drivers/common/qat/qat_device.h
> +++ b/drivers/common/qat/qat_device.h
> @@ -20,6 +20,8 @@
> #define SYM_ENQ_THRESHOLD_NAME "qat_sym_enq_threshold"
> #define ASYM_ENQ_THRESHOLD_NAME "qat_asym_enq_threshold"
> #define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
> +#define QAT_CMD_SLICE_MAP "qat_slice_disable"
[KJ] consider to rename the command to match the #define name
> +#define QAT_CMD_SLICE_MAP_POS 4
> #define MAX_QP_THRESHOLD_SIZE 32
>
<snip>
>
> extern struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[]; diff --git
> a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
> b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
> index 4499fdaf2d..67b1892c32 100644
> --- a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
> +++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
> @@ -41,14 +41,42 @@ static struct rte_cryptodev_capabilities
> qat_asym_crypto_caps_gen1[] = {
> RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
> };
>
> -
> -struct qat_capabilities_info
> -qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev
> __rte_unused)
> +int
> +qat_asym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,
> + const char *capa_memz_name,
> + const uint16_t __rte_unused slice_map)
> {
> - struct qat_capabilities_info capa_info;
> - capa_info.data = qat_asym_crypto_caps_gen1;
> - capa_info.size = sizeof(qat_asym_crypto_caps_gen1);
> - return capa_info;
> + const uint32_t size = sizeof(qat_asym_crypto_caps_gen1);
> + uint32_t i;
> +
> + internals->capa_mz = rte_memzone_lookup(capa_memz_name);
> + if (internals->capa_mz == NULL) {
> + internals->capa_mz =
> rte_memzone_reserve(capa_memz_name,
> + size, rte_socket_id(), 0);
> + if (internals->capa_mz == NULL) {
> + QAT_LOG(DEBUG,
> + "Error allocating memzone for capabilities");
> + return -1;
[KJ] ENOMEM ?
> + }
> + }
> +
> + struct rte_cryptodev_capabilities *addr =
> + (struct rte_cryptodev_capabilities *)
> + internals->capa_mz->addr;
> + const struct rte_cryptodev_capabilities *capabilities =
> + qat_asym_crypto_caps_gen1;
> + const uint32_t capa_num =
> + size / sizeof(struct rte_cryptodev_capabilities);
> + uint32_t curr_capa = 0;
> +
> + for (i = 0; i < capa_num; i++) {
> + memcpy(addr + curr_capa, capabilities + i,
> + sizeof(struct rte_cryptodev_capabilities));
> + curr_capa++;
> + }
> + internals->qat_dev_capabilities = internals->capa_mz->addr;
> +
> + return 0;
> }
>
> uint64_t
> diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
> b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
> index 0c64c1e43f..3d01fa7770 100644
> --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
> +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
> @@ -275,13 +275,42 @@ struct rte_cryptodev_ops
> qat_sym_crypto_ops_gen2 = {
> .sym_configure_raw_dp_ctx = qat_sym_configure_dp_ctx, };
>
> -static struct qat_capabilities_info
> -qat_sym_crypto_cap_get_gen2(struct qat_pci_device *qat_dev
> __rte_unused)
> +static int
> +qat_sym_crypto_cap_get_gen2(struct qat_cryptodev_private *internals,
> + const char *capa_memz_name,
> + const uint16_t __rte_unused slice_map)
> {
> - struct qat_capabilities_info capa_info;
> - capa_info.data = qat_sym_crypto_caps_gen2;
> - capa_info.size = sizeof(qat_sym_crypto_caps_gen2);
> - return capa_info;
> + const uint32_t size = sizeof(qat_sym_crypto_caps_gen2);
> + uint32_t i;
> +
> + internals->capa_mz = rte_memzone_lookup(capa_memz_name);
> + if (internals->capa_mz == NULL) {
> + internals->capa_mz =
> rte_memzone_reserve(capa_memz_name,
> + size, rte_socket_id(), 0);
> + if (internals->capa_mz == NULL) {
> + QAT_LOG(DEBUG,
> + "Error allocating memzone for capabilities");
> + return -1;
[KJ] ENOMEM ?
> + }
> + }
> +
> + struct rte_cryptodev_capabilities *addr =
> + (struct rte_cryptodev_capabilities *)
> + internals->capa_mz->addr;
> + const struct rte_cryptodev_capabilities *capabilities =
> + qat_sym_crypto_caps_gen2;
> + const uint32_t capa_num =
> + size / sizeof(struct rte_cryptodev_capabilities);
> + uint32_t curr_capa = 0;
> +
> + for (i = 0; i < capa_num; i++) {
> + memcpy(addr + curr_capa, capabilities + i,
> + sizeof(struct rte_cryptodev_capabilities));
> + curr_capa++;
> + }
> + internals->qat_dev_capabilities = internals->capa_mz->addr;
> +
> + return 0;
> }
>
> RTE_INIT(qat_sym_crypto_gen2_init)
> diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
> b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
> index d1285cdbd4..7f00f6097d 100644
> --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
> +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
> @@ -143,13 +143,81 @@ static struct rte_cryptodev_capabilities
<snip>
> +
> +static int
> +qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,
> + const char *capa_memz_name, const uint16_t
> slice_map) {
> + const uint32_t size = sizeof(qat_sym_crypto_caps_gen3);
> + uint32_t i;
> +
> + internals->capa_mz = rte_memzone_lookup(capa_memz_name);
> + if (internals->capa_mz == NULL) {
> + internals->capa_mz =
> rte_memzone_reserve(capa_memz_name,
> + size, rte_socket_id(), 0);
> + if (internals->capa_mz == NULL) {
> + QAT_LOG(DEBUG,
> + "Error allocating memzone for capabilities");
> + return -1;
[KJ] ENOMEM ?
> + }
> + }
> +
> + struct rte_cryptodev_capabilities *addr =
> + (struct rte_cryptodev_capabilities *)
> + internals->capa_mz->addr;
> + const struct rte_cryptodev_capabilities *capabilities =
> + qat_sym_crypto_caps_gen3;
> + const uint32_t capa_num =
> + size / sizeof(struct rte_cryptodev_capabilities);
> + uint32_t curr_capa = 0;
> +
> + for (i = 0; i < capa_num; i++) {
[KJ] can you add short comments why we need check SM4 & SM3 here ?
<snip>
>
> uint64_t
> diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
> index 19931791c4..486affb157 100644
> --- a/drivers/crypto/qat/qat_asym.c
> +++ b/drivers/crypto/qat/qat_asym.c
<snip>
>
> + if (slice_map & ICP_ACCEL_MASK_PKE_SLICE) {
> + QAT_LOG(ERR, "Device %s does not support PKE slice",
> + name);
> + rte_cryptodev_pmd_destroy(cryptodev);
> + memset(&qat_dev_instance->asym_rte_dev, 0,
> + sizeof(qat_dev_instance->asym_rte_dev));
> + return -1;
[KJ] EINVAL?
> + }
> +
> + if (gen_dev_ops->get_capabilities(internals,
> + capa_memz_name, slice_map) < 0) {
> + QAT_LOG(ERR,
> + "Device cannot obtain capabilties, destroying PMD
> for %s",
> + name);
> + rte_cryptodev_pmd_destroy(cryptodev);
> + memset(&qat_dev_instance->asym_rte_dev, 0,
> + sizeof(qat_dev_instance->asym_rte_dev));
> + return -1;
[KJ] EFAULT?
> + }
> +
> qat_pci_dev->asym_dev = internals;
> internals->service_type = QAT_SERVICE_ASYMMETRIC;
> QAT_LOG(DEBUG, "Created QAT ASYM device %s as cryptodev
> instance %d", diff --git a/drivers/crypto/qat/qat_crypto.h
> b/drivers/crypto/qat/qat_crypto.h index cf386d0ed0..6fe1326c51 100644
> --- a/drivers/crypto/qat/qat_crypto.h
> +++ b/drivers/crypto/qat/qat_crypto.h
> @@ -44,8 +44,8 @@ struct qat_capabilities_info {
> uint64_t size;
> };
>
> -typedef struct qat_capabilities_info (*get_capabilities_info_t)
> - (struct qat_pci_device *qat_dev);
> +typedef int (*get_capabilities_info_t)(struct qat_cryptodev_private
> *internals,
> + const char *capa_memz_name, uint16_t slice_map);
>
> typedef uint64_t (*get_feature_flags_t)(struct qat_pci_device *qat_dev);
>
> diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
> index 54c3d59a51..79f8a0b74f 100644
> --- a/drivers/crypto/qat/qat_sym.c
> +++ b/drivers/crypto/qat/qat_sym.c
> @@ -182,6 +182,7 @@ qat_sym_dev_create(struct qat_pci_device
> *qat_pci_dev,
> struct qat_dev_cmd_param *qat_dev_cmd_param
> __rte_unused) {
> int i = 0, ret = 0;
> + uint16_t slice_map = 0;
> struct qat_device_info *qat_dev_instance =
> &qat_pci_devs[qat_pci_dev->qat_dev_id];
> struct rte_cryptodev_pmd_init_params init_params = { @@ -193,11
> +194,8 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
> char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];
> struct rte_cryptodev *cryptodev;
> struct qat_cryptodev_private *internals;
> - struct qat_capabilities_info capa_info;
> - const struct rte_cryptodev_capabilities *capabilities;
> const struct qat_crypto_gen_dev_ops *gen_dev_ops =
> &qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen];
> - uint64_t capa_size;
>
> snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
> qat_pci_dev->name, "sym");
> @@ -277,37 +275,25 @@ qat_sym_dev_create(struct qat_pci_device
> *qat_pci_dev,
>
> internals->dev_id = cryptodev->data->dev_id;
>
> - capa_info = gen_dev_ops->get_capabilities(qat_pci_dev);
> - capabilities = capa_info.data;
> - capa_size = capa_info.size;
> -
> - internals->capa_mz = rte_memzone_lookup(capa_memz_name);
> - if (internals->capa_mz == NULL) {
> - internals->capa_mz =
> rte_memzone_reserve(capa_memz_name,
> - capa_size, rte_socket_id(), 0);
> - if (internals->capa_mz == NULL) {
> - QAT_LOG(DEBUG,
> - "Error allocating memzone for capabilities, "
> - "destroying PMD for %s", name);
> - ret = -EFAULT;
> - goto error;
> - }
> - }
> -
> - memcpy(internals->capa_mz->addr, capabilities, capa_size);
> - internals->qat_dev_capabilities = internals->capa_mz->addr;
> -
> - while (1) {
> - if (qat_dev_cmd_param[i].name == NULL)
> - break;
> + while (qat_dev_cmd_param[i].name != NULL) {
> if (!strcmp(qat_dev_cmd_param[i].name,
> SYM_ENQ_THRESHOLD_NAME))
> internals->min_enq_burst_threshold =
> qat_dev_cmd_param[i].val;
> if (!strcmp(qat_dev_cmd_param[i].name,
> QAT_IPSEC_MB_LIB))
> qat_ipsec_mb_lib = qat_dev_cmd_param[i].val;
> + if (!strcmp(qat_dev_cmd_param[i].name,
> QAT_CMD_SLICE_MAP))
> + slice_map = qat_dev_cmd_param[i].val;
> i++;
> }
>
> + if (gen_dev_ops->get_capabilities(internals,
> + capa_memz_name, slice_map) < 0) {
> + QAT_LOG(ERR,
> + "Device cannot obtain capabilties, destroying PMD
> for %s",
> + name);
> + ret = -1;
> + goto error;
> + }
> internals->service_type = QAT_SERVICE_SYMMETRIC;
> qat_pci_dev->sym_dev = internals;
> QAT_LOG(DEBUG, "Created QAT SYM device %s as cryptodev
> instance %d",
> --
> 2.13.6
prev parent reply other threads:[~2022-10-16 22:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 14:02 Arek Kusztal
2022-10-14 10:28 ` [EXT] " Akhil Goyal
2022-10-16 22:24 ` Ji, Kai [this message]
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