From: Bruce Richardson <bruce.richardson@intel.com>
To: "Mattias Rönnblom" <hofors@lysator.liu.se>
Cc: "Morten Brørup" <mb@smartsharesystems.com>,
konstantin.v.ananyev@yandex.ru, Honnappa.Nagarahalli@arm.com,
stephen@networkplumber.org, mattias.ronnblom@ericsson.com,
kda@semihalf.com, drc@linux.vnet.ibm.com, dev@dpdk.org
Subject: Re: [PATCH] eal: non-temporal memcpy
Date: Mon, 10 Oct 2022 10:57:52 +0100 [thread overview]
Message-ID: <Y0PsoPM6CctmKyWo@bricha3-MOBL.ger.corp.intel.com> (raw)
In-Reply-To: <730193b1-9574-ff59-28be-c1449cba0ffc@lysator.liu.se>
On Mon, Oct 10, 2022 at 10:58:57AM +0200, Mattias Rönnblom wrote:
> On 2022-10-10 09:35, Morten Brørup wrote:
> > Mattias, Konstantin, Honnappa, Stephen,
> >
> > In my patch for non-temporal memcpy, I have been aiming for using as much non-temporal store as possible. E.g. copying 16 byte to a 16 byte aligned address will be done using non-temporal store instructions.
> >
> > Now, I am seriously considering this alternative:
> >
> > Only using non-temporal stores for complete cache lines, and using normal stores for partial cache lines.
> >
>
> This is how I've done it in the past, in DPDK applications. That was both to
> simplify (and potentially optimize) the code somewhat, and because I had my
> doubt there was any actual benefits from using non-temporal stores for the
> beginning or the end of the memory block.
>
> That latter reason however, was pure conjecture. I think it would be great
> if Intel, ARM, AMD, IBM etc. DPDK developers could dig in the manuals or go
> find the appropriate CPU expert, to find out if that is true.
>
> More specifically, my question is:
>
> A) Consider a scenario where a core does a regular store against some cache
> line, and then pretty much immediately does a non-temporal store against a
> different address in the same cache line. How will this cache line be
> treated?
>
> B) Consider the same scenario, but where no regular stores preceded (or
> followed) the non-temporal store, and the non-temporal stores performed did
> not cover the entirety of the cache line.
>
The best reference I am aware of for this for Intel CPUs is section
10.4.6.2 in Vol 1 of the Software Developers Manual[1].
The bit relevant to your scenarios above is:
"If a program specifies a non-temporal store with one of these instruc-
tions and the memory type of the destination region is write back (WB), write through (WT), or write combining
(WC), the processor will do the following:
• If the memory location being written to is present in the cache hierarchy, the data in the caches is evicted.
• The non-temporal data is written to memory with WC semantics"
Hope this helps a little.
Regards,
/Bruce
[1] https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf#G11.44032
next prev parent reply other threads:[~2022-10-10 9:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-19 13:58 [RFC v3] " Morten Brørup
2022-10-06 20:34 ` [PATCH] eal: " Morten Brørup
2022-10-10 7:35 ` Morten Brørup
2022-10-10 8:58 ` Mattias Rönnblom
2022-10-10 9:36 ` Morten Brørup
2022-10-10 11:58 ` Stanislaw Kardach
2022-10-10 9:57 ` Bruce Richardson [this message]
2022-10-11 9:25 ` Konstantin Ananyev
2022-10-07 10:19 ` [PATCH v2] " Morten Brørup
2022-10-09 15:35 ` [PATCH v3] " Morten Brørup
2022-10-10 6:46 ` [PATCH v4] " Morten Brørup
2022-10-16 14:27 ` Mattias Rönnblom
2022-10-16 19:55 ` Mattias Rönnblom
2023-07-31 12:14 ` Thomas Monjalon
2023-07-31 12:25 ` Morten Brørup
2023-08-04 5:49 ` Mattias Rönnblom
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y0PsoPM6CctmKyWo@bricha3-MOBL.ger.corp.intel.com \
--to=bruce.richardson@intel.com \
--cc=Honnappa.Nagarahalli@arm.com \
--cc=dev@dpdk.org \
--cc=drc@linux.vnet.ibm.com \
--cc=hofors@lysator.liu.se \
--cc=kda@semihalf.com \
--cc=konstantin.v.ananyev@yandex.ru \
--cc=mattias.ronnblom@ericsson.com \
--cc=mb@smartsharesystems.com \
--cc=stephen@networkplumber.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).