From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 94E0445EC3; Mon, 16 Dec 2024 20:41:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7221A402AC; Mon, 16 Dec 2024 20:41:29 +0100 (CET) Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) by mails.dpdk.org (Postfix) with ESMTP id 42B77402A3 for ; Mon, 16 Dec 2024 20:41:28 +0100 (CET) Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-2161eb94cceso30249855ad.2 for ; Mon, 16 Dec 2024 11:41:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1734378087; x=1734982887; darn=dpdk.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=f/wwjO0whimTHL7d8RBlRFJ5KbWCIa1rZdQ/ef7VK7k=; b=HHBZFPQVxFfHed4wOMrFj6+wrnoW35YxUJ6Jwhl+v4VfPxXxQWdnSzK+HmEDc3lFZE J40hSMVZjqu6WP7Z3IioKGJshEr7gD/sVCAgYhjysc0KS3PxDL8XbuKsMH5ADgKNEfE7 iOvZrvwqfWfldz0lNTYavtBVBWe3uL3fejWQs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734378087; x=1734982887; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=f/wwjO0whimTHL7d8RBlRFJ5KbWCIa1rZdQ/ef7VK7k=; b=Z/njy8QTNpV5t2/H01aWJQWpXIfIU3TEOa6AkfhFzFh+lFQkQXvIFt6s7O90FQUVHH 2UvJPGCMgSuLe34xhettOPMYID0X53LYV7ebZHXHzyS2dh+vh+JxGFImczXiPDFBo20q r+Kzto2tqRbdqGksvmLiE0IZLNbs/UQZGy6AoEtpgkMMJ2+odDIE1Ek+CDOIrXB9GnKy WJod3oNwLKkpQKO5RyAKjQqccTsf+B+cXWHQRUDMPit7mT7pCqOfiy59HfdJ8VqsUHr8 dww2qxhC1PNpnZ61wbcdbVUk8JvoehUZG6HXHQ6O6t0CmNGruMEgmaLHjUBnW1z9qaAA Lyhw== X-Forwarded-Encrypted: i=1; AJvYcCWMHqxguiwu/Kl8x6B7SPSoMREXGnCFryS7Xv4Lk3kHdLcuHyogK7d9onhb3s1nGNZIpA==@dpdk.org X-Gm-Message-State: AOJu0YzqcTrCLXElhqAfmD/Sg0bGJnmeBWZTeuQQmtCmkDsOxfmm8Px2 MiXMbscfz5x15R58EwvAr/Ff8AuNoscPKuIMaKRCmh9QmXJRBib6VDGKDFB2qXrKfDrojpMCT+S RnnWYudgQf97qdi5szaGyQt/+QSG/5yZ+sxGD/Q== X-Gm-Gg: ASbGncuiw4x1JoAd2EFUUHM490qWSmdHrcXD7AF5kS2rX5sCyR2P0K+ZljRnA+6eZJZ ue6csxPc7iJLQCG4y5rDEdRm4ysT+SgEld0qqqKVDRKH30TRKsn5MDwVzuCo3qQhYw49zDJc= X-Google-Smtp-Source: AGHT+IGrcj2heN202hi1gLPLW0kBBFp/ZULl/CD4T9Py8LfK20Ox3FA46RZcmP8wjsqfgqaWJDWic+L38QVIvs/c4XI= X-Received: by 2002:a17:90b:2803:b0:2ee:d824:b559 with SMTP id 98e67ed59e1d1-2f2d7f81d9dmr961151a91.28.1734378087143; Mon, 16 Dec 2024 11:41:27 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Patrick Robb Date: Mon, 16 Dec 2024 14:39:03 -0500 Message-ID: Subject: Re: [EXTERNAL] CN10K Crypto Test Issue To: Hiral Shah Cc: Cody Cheng , Gnanesh Kambalu Palanethra , JogaRao Nartu , Bharath Rajendra , "ci@dpdk.org" Content-Type: multipart/alternative; boundary="000000000000ca7adf0629685d42" X-BeenThere: ci@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK CI discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: ci-bounces@dpdk.org --000000000000ca7adf0629685d42 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks, just confirming is this pacific time? On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah wrot= e: > Sure! > > We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM. > > > Regards, > Hiral > ------------------------------ > *From:* Patrick Robb > *Sent:* Monday, December 16, 2024 10:55 AM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > Hi Hiral, The cnxk crypto device VF creation and driver binding steps tha= t > Cody wrote in his email are actually straight from the SDK document. > Specifically he followed the steps from doc-base-SDK12. 24. > 11/dpdk/pmd/rte_cryptodev. html#initialization > Hi Hiral, > > The cnxk crypto device VF creation and driver binding steps that Cody > wrote in his email are actually straight from the SDK document. > Specifically he followed the steps > from doc-base-SDK12.24.11/dpdk/pmd/rte_cryptodev.html#initialization > > Thanks for offering a sync up - this would be ideal as we are still stuck= . > We can schedule a Zoom and invite you. Do I remember correctly that you a= re > in the pacific time zone? Is any particular day this week good for you? > > Thanks for all the help. > -Patrick > > On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah wr= ote: > > Hi Cody, > > Can you please refer our SDK document? It should have clear instructions. > We can sync up if you still have any questions. > > Regards, > Hiral > ------------------------------ > *From:* Cody Cheng > *Sent:* Friday, December 13, 2024 11:47 AM > *To:* Gnanesh Kambalu Palanethra ; Hiral Shah < > hshah@marvell.com> > *Cc:* JogaRao Nartu ; Bharath Rajendra < > brajendra@marvell.com>; Patrick Robb ; ci@dpdk.org < > ci@dpdk.org> > *Subject:* [EXTERNAL] CN10K Crypto Test Issue > > Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the University > of New Hampshire DPDK Community Test Lab. We are hosting a CN10K board he= re > which is currently running some ethernet device tests on DPDK, and we wou= ld > like to extend > > Hi Gnanesh & Hiral, > > My name is Cody Cheng, I'm a tester at the University of New Hampshire > DPDK Community Test Lab. We are hosting a CN10K board here which is > currently running some ethernet device tests on DPDK, and we would > like to extend our testing to include crypto device testing. Gnanesh > has written a patch which adds testcases to the DPDK Test Suite which > should allow us to do so. > > However, I am running into difficulties with the crypto devices I > create in DPDK from the CN10K board. I would appreciate it if I can > sync with one of you next week so that I can show our current > configuration, and run through the DPDK crypto device setup process > and CN10K autotest (not passing currently). I am guessing there is > some error in our configuration. My coworker Patrick Robb has > mentioned he met with Hiral previously and it was a big help for > understanding how to flash the correct firmware, build the SDK and > tftpboot it, chroot to Ubuntu etc. I hope we can do something similar > to clear up the confusion regarding crypto devs. What timezones are > you in? I would be happy to schedule a Zoom call. > > Otherwise, I will share some of the system info and the process I have > run through below, which might begin to give you an idea regarding our > status: > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Marvell CN10k Boot Stub > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Firmware Version: 2024-12-07 02:04:42 > EBF Version: 12.24.11, Branch: > /MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-external= -fw-SDK12.24.11/firmware/ebf, > Built: Sat, 07 Dec 2024 02:02:27 +0000 > > Board Model: crb106 > Board Revision: r1p1 > Board Serial: > > Chip: 0xb9 Pass A1 > SKU: MV-CN10624-A1-AAP > LLC: 49152 KB > Boot: SPI1_CS0,EMMC_CS0, using SPI1_CS0 > AVS: Enabled > > I am setting up 1 crypto virtual function using the commands here:https:/= /urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guides_cryptod= evs_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOyPaz7xtfQ&r=3DvG= y6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwgTF6BzuBPsPbKfZfmAua-fox= lSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFSGcAGResAexjf_pFNDJ0Szm68pM2= tw5BFzUM&e=3D > > So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1 > > At this stage, according to the docs I should be able to launch > dpdk-test and run the cn10k symmetrical crypto autotest, using the > commands below: > > ``` > ./dpdk-test > RTE>>cryptodev_cn10k_autotest > ``` > > However, the auto tests fail and fall into an error loop which I have > attached the logs of in this email. > > Here is the EAL output from the logs: > > EAL: Detected CPU lcores: 24 > EAL: Detected NUMA nodes: 1 > EAL: Detected static linkage of DPDK > EAL: Multi-process socket /var/run/dpdk/rte/mp_socket > EAL: Selected IOVA mode 'VA' > EAL: VFIO support initialized > EAL: Using IOMMU type 1 (Type 1) > CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM) > CRYPTODEV: Creating cryptodev 0002:20:00.1 > CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id: > 0, max queue pairs: 0 > APP: HPET is not enabled, using TSC as default timer > > In the EAL output, max queue pairs is 0 even though in the docs, it > says the Maximum queue pairs limit is set to a default of 63. Could > this be related to the issue? > > Also, here is my kernel cmdline parameters: > > console=3DttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24 > rootwait root=3D/dev/nvme0n1p1 rw coherent_pool=3D16M > default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8 > > Does this look correct? > > I have also tried setting `iommu.passthrough=3D1` in the boot arguments > but that resulted in the same dpdk-test failure. > > Best Regards, > Cody Cheng > > --000000000000ca7adf0629685d42 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thanks, just confirming is this pacific time?

On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah <hshah@marvell.com> wrote:
Sure!

We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM.=C2= =A0


Regards,
Hiral
From:= Patrick Robb <pr= obb@iol.unh.edu>
Sent: Monday, December 16, 2024 10:55 AM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com&g= t;; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
Hi Hiral, The cnxk crypto device VF creation and driver binding steps that = Cody wrote in his email are actually straight from the SDK document. Specif= ically he followed the steps from doc-base-SDK12.=E2=80=8A24.=E2=80=8A11/dp= dk/pmd/rte_cryptodev.=E2=80=8Ahtml#initialization
Hi Hiral,

The cnxk=C2=A0crypto device VF creation and driver binding steps that = Cody wrote in his email are actually straight from the SDK document. Specif= ically he followed the steps from=C2=A0doc-base-SDK12.24.11/dpdk/pmd/rte_cr= yptodev.html#initialization

Thanks for offering a sync up - this would be ideal as we are still st= uck. We can schedule a Zoom and invite you. Do I remember correctly that yo= u are in the pacific time zone? Is any particular day this week good for yo= u?=C2=A0

Thanks for all the help.
-Patrick

On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah <hshah@marvell.com&g= t; wrote:
Hi Cody,=C2=A0

Can you please refer our SDK document? It should have clear instructions. W= e can sync up if you still have any questions.=C2=A0

Regards,
Hiral
From: Cody Cheng <ccheng@iol.unh.edu>
Sent: Friday, December 13, 2024 11:47 AM
To: Gnanesh Kambalu Palanethra <gpalanethra@marvell.com>; Hiral Shah <= ;hshah@marvell.com>
Cc: JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>= ;; Patrick Robb <= probb@iol.unh.edu>; ci@dpdk.org <ci@dpdk.org>
Subject: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the Univ= ersity of New Hampshire DPDK Community Test Lab. We are hosting a CN10K boa= rd here which is currently running some ethernet device tests on DPDK, and = we would like to extend
H=
i Gnanesh & Hiral,

My name is Cody Cheng, I'm a tester at the University of New Hampshire
DPDK Community Test Lab. We are hosting a CN10K board here which is
currently running some ethernet device tests on DPDK, and we would
like to extend our testing to include crypto device testing. Gnanesh
has written a patch which adds testcases to the DPDK Test Suite which
should allow us to do so.

However, I am running into difficulties with the crypto devices I
create in DPDK from the CN10K board. I would appreciate it if I can
sync with one of you next week so that I can show our current
configuration, and run through the DPDK crypto device setup process
and CN10K autotest (not passing currently). I am guessing there is
some error in our configuration. My coworker Patrick Robb has
mentioned he met with Hiral previously and it was a big help for
understanding how to flash the correct firmware, build the SDK and
tftpboot it, chroot to Ubuntu etc. I hope we can do something similar
to clear up the confusion regarding crypto devs. What timezones are
you in? I would be happy to schedule a Zoom call.

Otherwise, I will share some of the system info and the process I have
run through below, which might begin to give you an idea regarding our
status:

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Marvell CN10k Boot Stub
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Firmware Version: 2024-12-07 02:04:42
EBF Version: 12.24.11, Branch:
/MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-external-f=
w-SDK12.24.11/firmware/ebf,
Built: Sat, 07 Dec 2024 02:02:27 +0000

Board Model:    crb106
Board Revision: r1p1
Board Serial:   <redacted>

Chip:  0xb9 Pass A1
SKU:   MV-CN10624-A1-AAP
LLC:   49152 KB
Boot:  SPI1_CS0,EMMC_CS0, using SPI1_CS0
AVS:   Enabled

I am setting up 1 crypto virtual function using the commands here:
=
https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guides_=
cryptodevs_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOy=
Paz7xtfQ&r=3DvGy6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwg=
TF6BzuBPsPbKfZfmAua-foxlSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFS=
GcAGResAexjf_pFNDJ0Szm68pM2tw5BFzUM&e=3D

So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1

At this stage, according to the docs I should be able to launch
dpdk-test and run the cn10k symmetrical crypto autotest, using the
commands below:

```
./dpdk-test
RTE>>cryptodev_cn10k_autotest
```

However, the auto tests fail and fall into an error loop which I have
attached the logs of in this email.

Here is the EAL output from the logs:

EAL: Detected CPU lcores: 24
EAL: Detected NUMA nodes: 1
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM)
CRYPTODEV: Creating cryptodev 0002:20:00.1
CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id:
0, max queue pairs: 0
APP: HPET is not enabled, using TSC as default timer

In the EAL output, max queue pairs is 0 even though in the docs, it
says the Maximum queue pairs limit is set to a default of 63. Could
this be related to the issue?

Also, here is my kernel cmdline parameters:

console=3DttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24
rootwait root=3D/dev/nvme0n1p1 rw coherent_pool=3D16M
default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8

Does this look correct?

I have also tried setting `iommu.passthrough=3D1` in the boot arguments
but that resulted in the same dpdk-test failure.

Best Regards,
Cody Cheng
--000000000000ca7adf0629685d42--