Thanks Hiral for the offer of help, here is a zoom invite for a meeting from 1pm-2pm PST today (in 10 minutes). Sorry for the last notice, I can certainly reschedule if needed. Patrick Robb is inviting you to a scheduled Zoom meeting. Topic: Marvell DPDK Cryptodev sync Time: Dec 16, 2024 04:00 PM Eastern Time (US and Canada) Join from PC, Mac, Linux, iOS or Android: https://unh.zoom.us/j/99749831096 Keyboard shortcuts are available to navigate this Zoom meeting or webinar: https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard-for-Zoom Or iPhone one-tap: 16468769923,99749831096# or 16469313860,99749831096# Or Telephone: Dial: +1 646 876 9923 (US Toll) Meeting ID: 997 4983 1096 International numbers available: https://unh.zoom.us/u/aAZFiJCIr Or a H.323/SIP room system: H.323: rc.unh.edu or 144.195.19.161 (US West) or 206.247.11.121 (US East) Meeting ID: 997 4983 1096 SIP: 99749831096@zoomcrc.com TROUBLESHOOTING STEPS: Audio Echo In A Meeting: https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeting Want to Join a Test Meeting?: https://zoom.us/test On Mon, Dec 16, 2024 at 2:39 PM Patrick Robb wrote: > Thanks, just confirming is this pacific time? > > On Mon, Dec 16, 2024 at 2:27 PM Hiral Shah wrote: > >> Sure! >> >> We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM. >> >> >> Regards, >> Hiral >> ------------------------------ >> *From:* Patrick Robb >> *Sent:* Monday, December 16, 2024 10:55 AM >> *To:* Hiral Shah >> *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < >> gpalanethra@marvell.com>; JogaRao Nartu ; Bharath >> Rajendra ; ci@dpdk.org >> *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue >> >> Hi Hiral, The cnxk crypto device VF creation and driver binding steps >> that Cody wrote in his email are actually straight from the SDK document. >> Specifically he followed the steps from doc-base-SDK12. 24. >> 11/dpdk/pmd/rte_cryptodev. html#initialization >> Hi Hiral, >> >> The cnxk crypto device VF creation and driver binding steps that Cody >> wrote in his email are actually straight from the SDK document. >> Specifically he followed the steps >> from doc-base-SDK12.24.11/dpdk/pmd/rte_cryptodev.html#initialization >> >> Thanks for offering a sync up - this would be ideal as we are still >> stuck. We can schedule a Zoom and invite you. Do I remember correctly that >> you are in the pacific time zone? Is any particular day this week good for >> you? >> >> Thanks for all the help. >> -Patrick >> >> On Mon, Dec 16, 2024 at 1:33 PM Hiral Shah wrote: >> >> Hi Cody, >> >> Can you please refer our SDK document? It should have clear instructions. >> We can sync up if you still have any questions. >> >> Regards, >> Hiral >> ------------------------------ >> *From:* Cody Cheng >> *Sent:* Friday, December 13, 2024 11:47 AM >> *To:* Gnanesh Kambalu Palanethra ; Hiral Shah < >> hshah@marvell.com> >> *Cc:* JogaRao Nartu ; Bharath Rajendra < >> brajendra@marvell.com>; Patrick Robb ; ci@dpdk.org < >> ci@dpdk.org> >> *Subject:* [EXTERNAL] CN10K Crypto Test Issue >> >> Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the University >> of New Hampshire DPDK Community Test Lab. We are hosting a CN10K board here >> which is currently running some ethernet device tests on DPDK, and we would >> like to extend >> >> Hi Gnanesh & Hiral, >> >> My name is Cody Cheng, I'm a tester at the University of New Hampshire >> DPDK Community Test Lab. We are hosting a CN10K board here which is >> currently running some ethernet device tests on DPDK, and we would >> like to extend our testing to include crypto device testing. Gnanesh >> has written a patch which adds testcases to the DPDK Test Suite which >> should allow us to do so. >> >> However, I am running into difficulties with the crypto devices I >> create in DPDK from the CN10K board. I would appreciate it if I can >> sync with one of you next week so that I can show our current >> configuration, and run through the DPDK crypto device setup process >> and CN10K autotest (not passing currently). I am guessing there is >> some error in our configuration. My coworker Patrick Robb has >> mentioned he met with Hiral previously and it was a big help for >> understanding how to flash the correct firmware, build the SDK and >> tftpboot it, chroot to Ubuntu etc. I hope we can do something similar >> to clear up the confusion regarding crypto devs. What timezones are >> you in? I would be happy to schedule a Zoom call. >> >> Otherwise, I will share some of the system info and the process I have >> run through below, which might begin to give you an idea regarding our >> status: >> >> ======================= >> Marvell CN10k Boot Stub >> ======================= >> Firmware Version: 2024-12-07 02:04:42 >> EBF Version: 12.24.11, Branch: >> /MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-external-fw-SDK12.24.11/firmware/ebf, >> Built: Sat, 07 Dec 2024 02:02:27 +0000 >> >> Board Model: crb106 >> Board Revision: r1p1 >> Board Serial: >> >> Chip: 0xb9 Pass A1 >> SKU: MV-CN10624-A1-AAP >> LLC: 49152 KB >> Boot: SPI1_CS0,EMMC_CS0, using SPI1_CS0 >> AVS: Enabled >> >> I am setting up 1 crypto virtual function using the commands here:https://urldefense.proofpoint.com/v2/url?u=https-3A__doc.dpdk.org_guides_cryptodevs_cnxk.html-23initialization&d=DwIBaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=vGy6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=dN2bwgTF6BzuBPsPbKfZfmAua-foxlSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=_d4kcuFSGcAGResAexjf_pFNDJ0Szm68pM2tw5BFzUM&e= >> >> So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1 >> >> At this stage, according to the docs I should be able to launch >> dpdk-test and run the cn10k symmetrical crypto autotest, using the >> commands below: >> >> ``` >> ./dpdk-test >> RTE>>cryptodev_cn10k_autotest >> ``` >> >> However, the auto tests fail and fall into an error loop which I have >> attached the logs of in this email. >> >> Here is the EAL output from the logs: >> >> EAL: Detected CPU lcores: 24 >> EAL: Detected NUMA nodes: 1 >> EAL: Detected static linkage of DPDK >> EAL: Multi-process socket /var/run/dpdk/rte/mp_socket >> EAL: Selected IOVA mode 'VA' >> EAL: VFIO support initialized >> EAL: Using IOMMU type 1 (Type 1) >> CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM) >> CRYPTODEV: Creating cryptodev 0002:20:00.1 >> CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id: >> 0, max queue pairs: 0 >> APP: HPET is not enabled, using TSC as default timer >> >> In the EAL output, max queue pairs is 0 even though in the docs, it >> says the Maximum queue pairs limit is set to a default of 63. Could >> this be related to the issue? >> >> Also, here is my kernel cmdline parameters: >> >> console=ttyAMA0,115200n8 earlycon=p1011,0x87e028000000 maxcpus=24 >> rootwait root=/dev/nvme0n1p1 rw coherent_pool=16M >> default_hugepagesz=512M hugepagesz=512M hugepages=8 >> >> Does this look correct? >> >> I have also tried setting `iommu.passthrough=1` in the boot arguments >> but that resulted in the same dpdk-test failure. >> >> Best Regards, >> Cody Cheng >> >>