From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2110F45EC3; Mon, 16 Dec 2024 21:54:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 00B18402AC; Mon, 16 Dec 2024 21:54:11 +0100 (CET) Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) by mails.dpdk.org (Postfix) with ESMTP id A345B402A3 for ; Mon, 16 Dec 2024 21:54:09 +0100 (CET) Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-7fd45005a09so2753035a12.2 for ; Mon, 16 Dec 2024 12:54:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1734382449; x=1734987249; darn=dpdk.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=yzPQ22ar4urNKbJiV8hZuZNOyae4SDlT20boeBoGOio=; b=Ba+t+vFs/oUaFcvubi7TW1jCEdbwBTlS5F4vcAITSOzhV8NiOAEX331HkQC2RFEPUG 0t/9RO3LMC57gr1nWZMqTG/cNBJiZbBqNE1Aczx5CzBIep5mGbAh4QHOFDxDzKzEqgbc C2nIF/Azvw+cOFG2L9Vun1zQFh6UO3KWA3URU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734382449; x=1734987249; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=yzPQ22ar4urNKbJiV8hZuZNOyae4SDlT20boeBoGOio=; b=DwAEdhVwZhWuHrouSgcQZAFdxg9Y52ExlY5FUBzQ2/fzFMwgEie/LlHauDVdiT9aKD Egq6SDc4WoAMuvj0rPEUhjRMP8sSmg+FdgwezPgsHzlRasEhDrL7Xpgfnd5RVKpNASRB aoG+rjsaEbdCXXGB3rd282XG8sPa0NPs0wGByU57xGFXn2JzhRdHcoWtyHFsuYPx17ul snuIt9PqM162kpVKa/vfB+M5MKhtrN3P0MOWsJikHNSh7DDqzQq4l/kvRVJI4Az6dOsK a+KBdXqn1UzUvSgpq4I/AsxY4eZtDJVaJwZRjN1Y1VtkOfobMMN6hpv3tmVdIkfK0oW5 7Rrg== X-Forwarded-Encrypted: i=1; AJvYcCXLhEOu6VT00VtgIWNt7rtHK/L3/WPdYUYsJEWOcxYCAA6vXOgbrptTE7P0ww5duKoCnQ==@dpdk.org X-Gm-Message-State: AOJu0YwnyL57Z/VI46e7lL1NHzMgP5IO53q5+7RtDaza/cdNhQxA8GII YQn7yUYRKiloKZiBaCJFIfXvCFC+2qjcQs8LefsLbZk4xAD44OI25yPkoHhaRGaA66JcZdUG/0d zJZqx7AgDgr4ahHuodVfe7QxmJenjphEUpFPxbYYC3L9JSdPiTXQ= X-Gm-Gg: ASbGncvN87AZj5P8DnAbcTTLC25xNpRAM+yyNiAtKW7wN8+l1KBd2jmznBs3WSO3+Ih Ne0zcP1azIy8MG9hHwAzpJLo3xLaEc0osPwpuP2OL0vivzT5DGka/fnxomN0bmE7I/9yvzU0= X-Google-Smtp-Source: AGHT+IH4SXztnZpOr7TQKANDANN7wyR83qNocC3ErVldAxPbMa6n8aYOv5N+BcjVtJjFu4CobzEoFFDxi7exJxbKc0Y= X-Received: by 2002:a17:90b:380a:b0:2ee:a04b:92ce with SMTP id 98e67ed59e1d1-2f2901b108cmr18070685a91.32.1734382448602; Mon, 16 Dec 2024 12:54:08 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Patrick Robb Date: Mon, 16 Dec 2024 15:51:45 -0500 Message-ID: Subject: Re: [EXTERNAL] CN10K Crypto Test Issue To: Hiral Shah Cc: Cody Cheng , Gnanesh Kambalu Palanethra , JogaRao Nartu , Bharath Rajendra , "ci@dpdk.org" Content-Type: multipart/alternative; boundary="000000000000c10c5706296961f4" X-BeenThere: ci@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK CI discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: ci-bounces@dpdk.org --000000000000c10c5706296961f4 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks Hiral for the offer of help, here is a zoom invite for a meeting from 1pm-2pm PST today (in 10 minutes). Sorry for the last notice, I can certainly reschedule if needed. Patrick Robb is inviting you to a scheduled Zoom meeting. Topic: Marvell DPDK Cryptodev sync Time: Dec 16, 2024 04:00 PM Eastern Time (US and Canada) Join from PC, Mac, Linux, iOS or Android: https://unh.zoom.us/j/99749831096 Keyboard shortcuts are available to navigate this Zoom meeting or webinar: https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard-f= or-Zoom Or iPhone one-tap: 16468769923,99749831096# or 16469313860,99749831096# Or Telephone: Dial: +1 646 876 9923 (US Toll) Meeting ID: 997 4983 1096 International numbers available: https://unh.zoom.us/u/aAZFiJCIr Or a H.323/SIP room system: H.323: rc.unh.edu or 144.195.19.161 (US West) or 206.247.11.121 (US East) Meeting ID: 997 4983 1096 SIP: 99749831096@zoomcrc.com TROUBLESHOOTING STEPS: Audio Echo In A Meeting: https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeting Want to Join a Test Meeting?: https://zoom.us/test On Mon, Dec 16, 2024 at 2:39=E2=80=AFPM Patrick Robb wr= ote: > Thanks, just confirming is this pacific time? > > On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah wr= ote: > >> Sure! >> >> We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM. >> >> >> Regards, >> Hiral >> ------------------------------ >> *From:* Patrick Robb >> *Sent:* Monday, December 16, 2024 10:55 AM >> *To:* Hiral Shah >> *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < >> gpalanethra@marvell.com>; JogaRao Nartu ; Bharath >> Rajendra ; ci@dpdk.org >> *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue >> >> Hi Hiral, The cnxk crypto device VF creation and driver binding steps >> that Cody wrote in his email are actually straight from the SDK document= . >> Specifically he followed the steps from doc-base-SDK12. 24. >> 11/dpdk/pmd/rte_cryptodev. html#initialization >> Hi Hiral, >> >> The cnxk crypto device VF creation and driver binding steps that Cody >> wrote in his email are actually straight from the SDK document. >> Specifically he followed the steps >> from doc-base-SDK12.24.11/dpdk/pmd/rte_cryptodev.html#initialization >> >> Thanks for offering a sync up - this would be ideal as we are still >> stuck. We can schedule a Zoom and invite you. Do I remember correctly th= at >> you are in the pacific time zone? Is any particular day this week good f= or >> you? >> >> Thanks for all the help. >> -Patrick >> >> On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah w= rote: >> >> Hi Cody, >> >> Can you please refer our SDK document? It should have clear instructions= . >> We can sync up if you still have any questions. >> >> Regards, >> Hiral >> ------------------------------ >> *From:* Cody Cheng >> *Sent:* Friday, December 13, 2024 11:47 AM >> *To:* Gnanesh Kambalu Palanethra ; Hiral Shah < >> hshah@marvell.com> >> *Cc:* JogaRao Nartu ; Bharath Rajendra < >> brajendra@marvell.com>; Patrick Robb ; ci@dpdk.org < >> ci@dpdk.org> >> *Subject:* [EXTERNAL] CN10K Crypto Test Issue >> >> Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the Universit= y >> of New Hampshire DPDK Community Test Lab. We are hosting a CN10K board h= ere >> which is currently running some ethernet device tests on DPDK, and we wo= uld >> like to extend >> >> Hi Gnanesh & Hiral, >> >> My name is Cody Cheng, I'm a tester at the University of New Hampshire >> DPDK Community Test Lab. We are hosting a CN10K board here which is >> currently running some ethernet device tests on DPDK, and we would >> like to extend our testing to include crypto device testing. Gnanesh >> has written a patch which adds testcases to the DPDK Test Suite which >> should allow us to do so. >> >> However, I am running into difficulties with the crypto devices I >> create in DPDK from the CN10K board. I would appreciate it if I can >> sync with one of you next week so that I can show our current >> configuration, and run through the DPDK crypto device setup process >> and CN10K autotest (not passing currently). I am guessing there is >> some error in our configuration. My coworker Patrick Robb has >> mentioned he met with Hiral previously and it was a big help for >> understanding how to flash the correct firmware, build the SDK and >> tftpboot it, chroot to Ubuntu etc. I hope we can do something similar >> to clear up the confusion regarding crypto devs. What timezones are >> you in? I would be happy to schedule a Zoom call. >> >> Otherwise, I will share some of the system info and the process I have >> run through below, which might begin to give you an idea regarding our >> status: >> >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >> Marvell CN10k Boot Stub >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >> Firmware Version: 2024-12-07 02:04:42 >> EBF Version: 12.24.11, Branch: >> /MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-externa= l-fw-SDK12.24.11/firmware/ebf, >> Built: Sat, 07 Dec 2024 02:02:27 +0000 >> >> Board Model: crb106 >> Board Revision: r1p1 >> Board Serial: >> >> Chip: 0xb9 Pass A1 >> SKU: MV-CN10624-A1-AAP >> LLC: 49152 KB >> Boot: SPI1_CS0,EMMC_CS0, using SPI1_CS0 >> AVS: Enabled >> >> I am setting up 1 crypto virtual function using the commands here:https:= //urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guides_crypto= devs_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOyPaz7xtfQ&r=3Dv= Gy6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwgTF6BzuBPsPbKfZfmAua-fo= xlSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFSGcAGResAexjf_pFNDJ0Szm68pM= 2tw5BFzUM&e=3D >> >> So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1 >> >> At this stage, according to the docs I should be able to launch >> dpdk-test and run the cn10k symmetrical crypto autotest, using the >> commands below: >> >> ``` >> ./dpdk-test >> RTE>>cryptodev_cn10k_autotest >> ``` >> >> However, the auto tests fail and fall into an error loop which I have >> attached the logs of in this email. >> >> Here is the EAL output from the logs: >> >> EAL: Detected CPU lcores: 24 >> EAL: Detected NUMA nodes: 1 >> EAL: Detected static linkage of DPDK >> EAL: Multi-process socket /var/run/dpdk/rte/mp_socket >> EAL: Selected IOVA mode 'VA' >> EAL: VFIO support initialized >> EAL: Using IOMMU type 1 (Type 1) >> CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM) >> CRYPTODEV: Creating cryptodev 0002:20:00.1 >> CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id: >> 0, max queue pairs: 0 >> APP: HPET is not enabled, using TSC as default timer >> >> In the EAL output, max queue pairs is 0 even though in the docs, it >> says the Maximum queue pairs limit is set to a default of 63. Could >> this be related to the issue? >> >> Also, here is my kernel cmdline parameters: >> >> console=3DttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24 >> rootwait root=3D/dev/nvme0n1p1 rw coherent_pool=3D16M >> default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8 >> >> Does this look correct? >> >> I have also tried setting `iommu.passthrough=3D1` in the boot arguments >> but that resulted in the same dpdk-test failure. >> >> Best Regards, >> Cody Cheng >> >> --000000000000c10c5706296961f4 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thanks Hiral for the offer of help, here is a zoom invite = for a meeting from 1pm-2pm PST today (in 10 minutes).

So= rry for the last notice, I can certainly reschedule if needed.
Patrick Robb is inviting you to a scheduled Zoom meeting.
=
Topic: Marvell DPDK Cryptodev sync
Time: Dec 16, 2024 04:00 PM Easte= rn Time (US and Canada)

Join from PC, Mac, Linux, iOS or Android: <= a href=3D"https://unh.zoom.us/j/99749831096">https://unh.zoom.us/j/99749831= 096

Keyboard shortcuts are available to navigate this Zoom meeti= ng or webinar: https://support.zoom.us/hc/en-us/article= s/205683899-Hot-Keys-and-Keyboard-for-Zoom
=C2=A0
Or iPhone one-t= ap: =C2=A016468769923,99749831096# or 16469313860,99749831096#

Or Te= lephone:
=C2=A0 =C2=A0 Dial: +1 646 876 9923 (US Toll)
=C2=A0 =C2=A0 = Meeting ID: 997 4983 1096
=C2=A0 =C2=A0 International numbers available= : https://unh.zoom.us/u/aAZFiJC= Ir

Or a H.323/SIP room system:
=C2=A0 =C2=A0 H.323: rc.unh.edu or 144.195.19.161 (US West) or 206.24= 7.11.121 (US East)
=C2=A0 =C2=A0 Meeting ID: 997 4983 1096
=C2=A0 = =C2=A0 SIP: 99749831096@zoomcrc.= com

TROUBLESHOOTING STEPS:

Audio Echo In A Meeting: https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A= -Meeting

Want to Join a Test Meeting?: https://zoom.us/test

On Mon, Dec 16,= 2024 at 2:39=E2=80=AFPM Patrick Robb <probb@iol.unh.edu> wrote:
Thanks, just confirming is this pacif= ic time?

On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah <hshah@marvell.com> wrote:=
Sure!

We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM.=C2= =A0


Regards,
Hiral
From: Patrick Robb <probb@iol.unh.edu>
Sent: Monday, December 16, 2024 10:55 AM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com&g= t;; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
Hi Hiral, The cnxk crypto device VF creation and driver binding steps that = Cody wrote in his email are actually straight from the SDK document. Specif= ically he followed the steps from doc-base-SDK12.=E2=80=8A24.=E2=80=8A11/dp= dk/pmd/rte_cryptodev.=E2=80=8Ahtml#initialization
Hi Hiral,

The cnxk=C2=A0crypto device VF creation and driver binding steps that = Cody wrote in his email are actually straight from the SDK document. Specif= ically he followed the steps from=C2=A0doc-base-SDK12.24.11/dpdk/pmd/rte_cr= yptodev.html#initialization

Thanks for offering a sync up - this would be ideal as we are still st= uck. We can schedule a Zoom and invite you. Do I remember correctly that yo= u are in the pacific time zone? Is any particular day this week good for yo= u?=C2=A0

Thanks for all the help.
-Patrick

On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah <hshah@marvell.com&g= t; wrote:
Hi Cody,=C2=A0

Can you please refer our SDK document? It should have clear instructions. W= e can sync up if you still have any questions.=C2=A0

Regards,
Hiral
From: Cody Cheng <ccheng@iol.unh.edu>
Sent: Friday, December 13, 2024 11:47 AM
To: Gnanesh Kambalu Palanethra <gpalanethra@marvell.com>; Hiral Shah <= ;hshah@marvell.com>
Cc: JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>= ;; Patrick Robb <= probb@iol.unh.edu>; ci@dpdk.org <ci@dpdk.org>
Subject: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the Univ= ersity of New Hampshire DPDK Community Test Lab. We are hosting a CN10K boa= rd here which is currently running some ethernet device tests on DPDK, and = we would like to extend
H=
i Gnanesh & Hiral,

My name is Cody Cheng, I'm a tester at the University of New Hampshire
DPDK Community Test Lab. We are hosting a CN10K board here which is
currently running some ethernet device tests on DPDK, and we would
like to extend our testing to include crypto device testing. Gnanesh
has written a patch which adds testcases to the DPDK Test Suite which
should allow us to do so.

However, I am running into difficulties with the crypto devices I
create in DPDK from the CN10K board. I would appreciate it if I can
sync with one of you next week so that I can show our current
configuration, and run through the DPDK crypto device setup process
and CN10K autotest (not passing currently). I am guessing there is
some error in our configuration. My coworker Patrick Robb has
mentioned he met with Hiral previously and it was a big help for
understanding how to flash the correct firmware, build the SDK and
tftpboot it, chroot to Ubuntu etc. I hope we can do something similar
to clear up the confusion regarding crypto devs. What timezones are
you in? I would be happy to schedule a Zoom call.

Otherwise, I will share some of the system info and the process I have
run through below, which might begin to give you an idea regarding our
status:

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Marvell CN10k Boot Stub
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Firmware Version: 2024-12-07 02:04:42
EBF Version: 12.24.11, Branch:
/MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-external-f=
w-SDK12.24.11/firmware/ebf,
Built: Sat, 07 Dec 2024 02:02:27 +0000

Board Model:    crb106
Board Revision: r1p1
Board Serial:   <redacted>

Chip:  0xb9 Pass A1
SKU:   MV-CN10624-A1-AAP
LLC:   49152 KB
Boot:  SPI1_CS0,EMMC_CS0, using SPI1_CS0
AVS:   Enabled

I am setting up 1 crypto virtual function using the commands here:
=
https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guides_=
cryptodevs_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOy=
Paz7xtfQ&r=3DvGy6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwg=
TF6BzuBPsPbKfZfmAua-foxlSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFS=
GcAGResAexjf_pFNDJ0Szm68pM2tw5BFzUM&e=3D

So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1

At this stage, according to the docs I should be able to launch
dpdk-test and run the cn10k symmetrical crypto autotest, using the
commands below:

```
./dpdk-test
RTE>>cryptodev_cn10k_autotest
```

However, the auto tests fail and fall into an error loop which I have
attached the logs of in this email.

Here is the EAL output from the logs:

EAL: Detected CPU lcores: 24
EAL: Detected NUMA nodes: 1
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM)
CRYPTODEV: Creating cryptodev 0002:20:00.1
CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id:
0, max queue pairs: 0
APP: HPET is not enabled, using TSC as default timer

In the EAL output, max queue pairs is 0 even though in the docs, it
says the Maximum queue pairs limit is set to a default of 63. Could
this be related to the issue?

Also, here is my kernel cmdline parameters:

console=3DttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24
rootwait root=3D/dev/nvme0n1p1 rw coherent_pool=3D16M
default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8

Does this look correct?

I have also tried setting `iommu.passthrough=3D1` in the boot arguments
but that resulted in the same dpdk-test failure.

Best Regards,
Cody Cheng
--000000000000c10c5706296961f4--