From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9E5D45EDF; Wed, 18 Dec 2024 20:01:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 82A9A40EE2; Wed, 18 Dec 2024 20:01:55 +0100 (CET) Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by mails.dpdk.org (Postfix) with ESMTP id D877640DF5 for ; Wed, 18 Dec 2024 20:01:53 +0100 (CET) Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-725ed193c9eso30166b3a.1 for ; Wed, 18 Dec 2024 11:01:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1734548513; x=1735153313; darn=dpdk.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ZqAXtueNL6hGJg8e85ce5pQrk3HpwpJorgsLCChrIuY=; b=RAkcEC9vzRAVcztTLPS2wfM9/wYGbDfOa9A0fGKFVPSkCauXAEgMoLn09Ju4Xr/X61 P5g3Bf2lkb5OnUtrXtlaAcbyWF9SBedqve54g8f8Xing4A6bfahaXNSkjA2rOk0K9ofo DyGYd7ZpPTkdKvDXFWQGzmZqK2CL9tbtXuQ7M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734548513; x=1735153313; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ZqAXtueNL6hGJg8e85ce5pQrk3HpwpJorgsLCChrIuY=; b=m87vBV4HZcazafYX7WKfJFn2AUI5X/IF6ztQLTpBjK3yw01FNmxoT0y0MVd15F83vC E0bPAt3XXupBWMoAc1TgSdqGMcZ2Y++4y3EukzaMmPrYrdrGp+z++OmXR8UVQy2WgTuy AXsYgJ9QO3Sdhez/nUYKECLrqDvPciErSyB4iZNQdmNDXhrv0RlgY7KSxBnOvHB3X+FW KFSdxGAxoevQypv59sBUnvvffA8/Nb3IsjkF4U0mkpDD7xe7bWgaXNmPS4qKjEkA3a1B CPkaX0o3621kX5l8L+jVdCRVqy2s+vGbBPGdBykd+j/rk35bx07muAR0kGmpmxNGLi4J bQ/A== X-Forwarded-Encrypted: i=1; AJvYcCWYUxHYgPez7rC0Zb/qqIO6N1JVjLgKgFWpmv53Dw0L0NZlMqOIFjcjMcETr8DYDwU/dw==@dpdk.org X-Gm-Message-State: AOJu0Yxr6KqYyuPLah+wdLvnwFaBCmun6zPd5bBgZZAukRAhoa8X6i3i 48UQUbNbvgogN+YrRCr7zVa7zszoaw6UAUrJPkgaMMTdKMT8JS898S1k6m6YarUe/o5kENdJAFQ 5+m7TSOroCThkwgYk2EbvlhuJtqYl1NhDbsbcPyUXKneBxdl5wkI= X-Gm-Gg: ASbGncsMGUIn8I9+dBPNwMNN9gL2lyliL1sGgrpn2qB37yb/hIoVFG39mDzEDr0c/RQ e2JIDpKqbG9gIaa5IaT3q3Mrk4Z2JIO9C6FIt8yyeEom3OOK65DJCTDS5bm3F8KxVTFsgXPc= X-Google-Smtp-Source: AGHT+IGesdN5SmTevu36Bgu+ACScF/A17uFqUkYHbucDdBogb25Y2bj0JwYAHBMErmwEFr0o1Owy/EG3/LoxLRcV4rg= X-Received: by 2002:a17:90b:2cc5:b0:2ea:7329:43 with SMTP id 98e67ed59e1d1-2f443bd585fmr573305a91.6.1734548512484; Wed, 18 Dec 2024 11:01:52 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Patrick Robb Date: Wed, 18 Dec 2024 13:59:26 -0500 Message-ID: Subject: Re: [EXTERNAL] CN10K Crypto Test Issue To: Hiral Shah Cc: Cody Cheng , Gnanesh Kambalu Palanethra , JogaRao Nartu , Bharath Rajendra , "ci@dpdk.org" , Akhil Goyal Content-Type: multipart/alternative; boundary="000000000000eeccd60629900b3d" X-BeenThere: ci@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK CI discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: ci-bounces@dpdk.org --000000000000eeccd60629900b3d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Bharath and others, Here is the download link to the dpdk-test produced with the native compile on the cn10k host: https://drive.google.com/file/d/127sIjCok3ErxAjrvfncWbv7BOmgL8m6D/view?usp= =3Dsharing Thanks, looking forward to hearing back from you about how a native build works on your setup. And, apologies for the late meeting time for you - I did not realize which time zone you were in. If it turns out that a followup meeting is required I will be sure to schedule it earlier in the day. I'm also adding the DPDK crypto tree maintainer (Akhil Goyal) to the CC list for this thread. Best, Patrick On Wed, Dec 18, 2024 at 12:53=E2=80=AFPM Hiral Shah wro= te: > > Looks like meeting is over. > > Thanks Bharath! > > Regards, > Hiral > ------------------------------ > *From:* Patrick Robb > *Sent:* Wednesday, December 18, 2024 9:45 AM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > No worries, Bharath and the others are demonstrating the driver binding > and autotest procedure. On Wed, Dec 18, 2024 at 12: 37 PM Hiral Shah marvell. com> wrote: Hi Cody, Patrick, Give me 10 -15 more meeting. I am = on > another call. > No worries, Bharath and the others are demonstrating the driver binding > and autotest procedure. > > On Wed, Dec 18, 2024 at 12:37=E2=80=AFPM Hiral Shah w= rote: > > Hi Cody, Patrick, > > Give me 10 -15 more meeting. I am on another call. > > > Regards, > Hiral > ------------------------------ > *From:* Patrick Robb > *Sent:* Monday, December 16, 2024 1:57 PM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > Hi Hiral, Sorry about the last minute planning today - I am scheduling a > call for us for Wednesday at 9: 30AM PST. Cody will be in class at that > time but I will be available and I believe I know all the details of his > issue. > -------------------------------------------------------------------------= ---------------------------------- > Hi Hiral, > > Sorry about the last minute planning today - I am scheduling a call for u= s > for Wednesday at 9:30AM PST. Cody will be in class at that time but I wil= l > be available and I believe I know all the details of his issue. > > > -------------------------------------------------------------------------= ---------------------------------- > > Patrick Robb is inviting you to a scheduled Zoom meeting. > > Topic: Marvell Crypto Sync > Time: Dec 18, 2024 12:30 PM Eastern Time (US and Canada) > > Join from PC, Mac, Linux, iOS or Android: > https://unh.zoom.us/j/93859170209 > > > Keyboard shortcuts are available to navigate this Zoom meeting or webinar= : > https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard= -for-Zoom > > > Or iPhone one-tap: 13052241968,93859170209# or 13092053325,93859170209# > > Or Telephone: > Dial: +1 305 224 1968 (US Toll) > Meeting ID: 938 5917 0209 > International numbers available: https://unh.zoom.us/u/acTtiNQKou > > > Or a H.323/SIP room system: > H.323: rc.unh.edu > > or 144.195.19.161 (US West) or 206.247.11.121 (US East) > Meeting ID: 938 5917 0209 > SIP: 93859170209@zoomcrc.com > > TROUBLESHOOTING STEPS: > > Audio Echo In A Meeting: > https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeti= ng > > > Want to Join a Test Meeting?: https://zoom.us/test > > > On Mon, Dec 16, 2024 at 3:51=E2=80=AFPM Patrick Robb = wrote: > > Thanks Hiral for the offer of help, here is a zoom invite for a meeting > from 1pm-2pm PST today (in 10 minutes). > > Sorry for the last notice, I can certainly reschedule if needed. > > Patrick Robb is inviting you to a scheduled Zoom meeting. > > Topic: Marvell DPDK Cryptodev sync > Time: Dec 16, 2024 04:00 PM Eastern Time (US and Canada) > > Join from PC, Mac, Linux, iOS or Android: > https://unh.zoom.us/j/99749831096 > > > Keyboard shortcuts are available to navigate this Zoom meeting or webinar= : > https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard= -for-Zoom > > > Or iPhone one-tap: 16468769923,99749831096# or 16469313860,99749831096# > > Or Telephone: > Dial: +1 646 876 9923 (US Toll) > Meeting ID: 997 4983 1096 > International numbers available: https://unh.zoom.us/u/aAZFiJCIr > > > Or a H.323/SIP room system: > H.323: rc.unh.edu > > or 144.195.19.161 (US West) or 206.247.11.121 (US East) > Meeting ID: 997 4983 1096 > SIP: 99749831096@zoomcrc.com > > TROUBLESHOOTING STEPS: > > Audio Echo In A Meeting: > https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeti= ng > > > Want to Join a Test Meeting?: https://zoom.us/test > > > On Mon, Dec 16, 2024 at 2:39=E2=80=AFPM Patrick Robb = wrote: > > Thanks, just confirming is this pacific time? > > On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah wr= ote: > > Sure! > > We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM. > > > Regards, > Hiral > ------------------------------ > *From:* Patrick Robb > *Sent:* Monday, December 16, 2024 10:55 AM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > Hi Hiral, The cnxk crypto device VF creation and driver binding steps tha= t > Cody wrote in his email are actually straight from the SDK document. > Specifically he followed the steps from doc-base-SDK12. 24. > 11/dpdk/pmd/rte_cryptodev. html#initialization > Hi Hiral, > > The cnxk crypto device VF creation and driver binding steps that Cody > wrote in his email are actually straight from the SDK document. > Specifically he followed the steps > from doc-base-SDK12.24.11/dpdk/pmd/rte_cryptodev.html#initialization > > Thanks for offering a sync up - this would be ideal as we are still stuck= . > We can schedule a Zoom and invite you. Do I remember correctly that you a= re > in the pacific time zone? Is any particular day this week good for you? > > Thanks for all the help. > -Patrick > > On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah wr= ote: > > Hi Cody, > > Can you please refer our SDK document? It should have clear instructions. > We can sync up if you still have any questions. > > Regards, > Hiral > ------------------------------ > *From:* Cody Cheng > *Sent:* Friday, December 13, 2024 11:47 AM > *To:* Gnanesh Kambalu Palanethra ; Hiral Shah < > hshah@marvell.com> > *Cc:* JogaRao Nartu ; Bharath Rajendra < > brajendra@marvell.com>; Patrick Robb ; ci@dpdk.org < > ci@dpdk.org> > *Subject:* [EXTERNAL] CN10K Crypto Test Issue > > Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the University > of New Hampshire DPDK Community Test Lab. We are hosting a CN10K board he= re > which is currently running some ethernet device tests on DPDK, and we wou= ld > like to extend > > Hi Gnanesh & Hiral, > > My name is Cody Cheng, I'm a tester at the University of New Hampshire > DPDK Community Test Lab. We are hosting a CN10K board here which is > currently running some ethernet device tests on DPDK, and we would > like to extend our testing to include crypto device testing. Gnanesh > has written a patch which adds testcases to the DPDK Test Suite which > should allow us to do so. > > However, I am running into difficulties with the crypto devices I > create in DPDK from the CN10K board. I would appreciate it if I can > sync with one of you next week so that I can show our current > configuration, and run through the DPDK crypto device setup process > and CN10K autotest (not passing currently). I am guessing there is > some error in our configuration. My coworker Patrick Robb has > mentioned he met with Hiral previously and it was a big help for > understanding how to flash the correct firmware, build the SDK and > tftpboot it, chroot to Ubuntu etc. I hope we can do something similar > to clear up the confusion regarding crypto devs. What timezones are > you in? I would be happy to schedule a Zoom call. > > Otherwise, I will share some of the system info and the process I have > run through below, which might begin to give you an idea regarding our > status: > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Marvell CN10k Boot Stub > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Firmware Version: 2024-12-07 02:04:42 > EBF Version: 12.24.11, Branch: > /MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-external= -fw-SDK12.24.11/firmware/ebf, > Built: Sat, 07 Dec 2024 02:02:27 +0000 > > Board Model: crb106 > Board Revision: r1p1 > Board Serial: > > Chip: 0xb9 Pass A1 > SKU: MV-CN10624-A1-AAP > LLC: 49152 KB > Boot: SPI1_CS0,EMMC_CS0, using SPI1_CS0 > AVS: Enabled > > I am setting up 1 crypto virtual function using the commands here:https:/= /urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guides_cryptod= evs_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOyPaz7xtfQ&r=3DvG= y6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwgTF6BzuBPsPbKfZfmAua-fox= lSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFSGcAGResAexjf_pFNDJ0Szm68pM2= tw5BFzUM&e=3D > > So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1 > > At this stage, according to the docs I should be able to launch > dpdk-test and run the cn10k symmetrical crypto autotest, using the > commands below: > > ``` > ./dpdk-test > RTE>>cryptodev_cn10k_autotest > ``` > > However, the auto tests fail and fall into an error loop which I have > attached the logs of in this email. > > Here is the EAL output from the logs: > > EAL: Detected CPU lcores: 24 > EAL: Detected NUMA nodes: 1 > EAL: Detected static linkage of DPDK > EAL: Multi-process socket /var/run/dpdk/rte/mp_socket > EAL: Selected IOVA mode 'VA' > EAL: VFIO support initialized > EAL: Using IOMMU type 1 (Type 1) > CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM) > CRYPTODEV: Creating cryptodev 0002:20:00.1 > CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id: > 0, max queue pairs: 0 > APP: HPET is not enabled, using TSC as default timer > > In the EAL output, max queue pairs is 0 even though in the docs, it > says the Maximum queue pairs limit is set to a default of 63. Could > this be related to the issue? > > Also, here is my kernel cmdline parameters: > > console=3DttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24 > rootwait root=3D/dev/nvme0n1p1 rw coherent_pool=3D16M > default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8 > > Does this look correct? > > I have also tried setting `iommu.passthrough=3D1` in the boot arguments > but that resulted in the same dpdk-test failure. > > Best Regards, > Cody Cheng > > --000000000000eeccd60629900b3d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Bharath and others,

Here is the down= load link to the dpdk-test produced with the native compile on the cn10k ho= st:=C2=A0https://drive.google.com/file/d/127sIjCok3Er= xAjrvfncWbv7BOmgL8m6D/view?usp=3Dsharing

Thank= s, looking forward=C2=A0to hearing back from you about how a native build w= orks on your setup. And, apologies for the late meeting time for you - I di= d not realize which time zone you were in. If it turns out that a followup = meeting is required I will be sure to schedule it earlier in the day.
=

I'm also adding the DPDK crypto tree maintainer (Ak= hil Goyal) to the CC list for this thread.

Best,
Patrick

On Wed, Dec 18, 2024 at 12:53= =E2=80=AFPM Hiral Shah <hshah@marve= ll.com> wrote:

Looks like meeting is over.=C2=A0

Thanks Bharath!

Regards,
Hiral
From: = Patrick Robb <pro= bb@iol.unh.edu>
Sent: Wednesday, December 18, 2024 9:45 AM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com&g= t;; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
No worries, Bharath and the others are demonstrating the driver binding and= autotest procedure. On Wed, Dec 18, 2024 at 12:=E2=80=8A37 PM Hiral Shah &= lt;hshah@=E2=80=8Amarvell.=E2=80=8Acom> wrote: Hi Cody, Patrick, Give me= 10 -15 more meeting. I am on another call.=E2=80=8A
No worries, Bharath and the others are demonstrating the d= river binding and autotest procedure.

On Wed, Dec 18, 2024 at 12:37=E2=80=AFPM Hiral Shah <hshah@marvell.com&= gt; wrote:
Hi Cody, Patrick,

Give me 10 -15 more meeting. I am on another call.=C2=A0


Regards,
Hiral
From: Patrick Robb <probb@iol.unh.edu>
Sent: Monday, December 16, 2024 1:57 PM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
Hi Hiral, Sorry about the last minute planning today - I am scheduling a ca= ll for us for Wednesday at 9:=E2=80=8A30AM PST. Cody will be in class at th= at time but I will be available and I believe I know all the details of his= issue. -------------------------------------------------------------------= ----------------------------------------
Hi Hiral,

Sorry about the last minute planning today - I am scheduling a call fo= r us for Wednesday at 9:30AM PST. Cody will be in class at that time but I = will be available and I believe I know all the details of his issue.=C2=A0<= /div>

----------------------------------------------------------------------= -------------------------------------

Patrick Robb is inviting you to a scheduled Zoom meeting.

Topic: Marvell Crypto Sync
Time: Dec 18, 2024 12:30 PM Eastern Time (US and Canada)

Join from PC, Mac, Linux, iOS or Android: https://unh.zoom.us/j/93859170209

Keyboard shortcuts are available to navigate this Zoom meeting or webinar: = https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard-f= or-Zoom
=C2=A0
Or iPhone one-tap: =C2=A013052241968,93859170209# or 13092053325,9385917020= 9#

Or Telephone:
=C2=A0 =C2=A0 Dial: +1 305 224 1968 (US Toll)
=C2=A0 =C2=A0 Meeting ID: 938 5917 0209
=C2=A0 =C2=A0 International numbers available: https://unh.zoom.us/u/acTtiNQKou

Or a H.323/SIP room system:
=C2=A0 =C2=A0 H.323: rc.unh.edu or 144.195.19.161 (US West) or 206.247.11.121 (US East)
=C2=A0 =C2=A0 Meeting ID: 938 5917 0209
=C2=A0 =C2=A0 SIP: 93859170209@zoomcrc.com

TROUBLESHOOTING STEPS:

Audio Echo In A Meeting: https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeting=

Want to Join a Test Meeting?: https://zoom.us/test

On Mon, Dec 16, 2024 at 3:51=E2=80=AFPM Patrick Robb <<= a href=3D"mailto:probb@iol.unh.edu" target=3D"_blank">probb@iol.unh.edu= > wrote:
Thanks Hiral for the offer of help, here is a zoom invite = for a meeting from 1pm-2pm PST today (in 10 minutes).

Sorry for the last notice, I can certainly reschedule if needed.

Patrick Robb is inviting you to a scheduled Zoom meeting.

Topic: Marvell DPDK Cryptodev sync
Time: Dec 16, 2024 04:00 PM Eastern Time (US and Canada)

Join from PC, Mac, Linux, iOS or Android: https://unh.zoom.us/j/99749831096

Keyboard shortcuts are available to navigate this Zoom meeting or webinar: = https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard-f= or-Zoom
=C2=A0
Or iPhone one-tap: =C2=A016468769923,99749831096# or 16469313860,9974983109= 6#

Or Telephone:
=C2=A0 =C2=A0 Dial: +1 646 876 9923 (US Toll)
=C2=A0 =C2=A0 Meeting ID: 997 4983 1096
=C2=A0 =C2=A0 International numbers available: https://unh.zoom.us/u/aAZFiJCIr

Or a H.323/SIP room system:
=C2=A0 =C2=A0 H.323: rc.unh.edu or 144.195.19.161 (US West) or 206.247.11.121 (US East)
=C2=A0 =C2=A0 Meeting ID: 997 4983 1096
=C2=A0 =C2=A0 SIP: 99749831096@zoomcrc.com

TROUBLESHOOTING STEPS:

Audio Echo In A Meeting: https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeting=

Want to Join a Test Meeting?: https://zoom.us/test

On Mon, Dec 16, 2024 at 2:39=E2=80=AFPM Patrick Robb <<= a href=3D"mailto:probb@iol.unh.edu" target=3D"_blank">probb@iol.unh.edu= > wrote:
Thanks, just confirming is this pacific time?

On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah <hshah@marvell.com&g= t; wrote:
Sure!

We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM.=C2= =A0


Regards,
Hiral
From: Patrick Robb <probb@iol.unh.edu>
Sent: Monday, December 16, 2024 10:55 AM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
Hi Hiral, The cnxk crypto device VF creation and driver binding steps that = Cody wrote in his email are actually straight from the SDK document. Specif= ically he followed the steps from doc-base-SDK12.=E2=80=8A24.=E2=80=8A11/dp= dk/pmd/rte_cryptodev.=E2=80=8Ahtml#initialization
Hi Hiral,

The cnxk=C2=A0crypto device VF creation and driver binding steps that = Cody wrote in his email are actually straight from the SDK document. Specif= ically he followed the steps from=C2=A0doc-base-SDK12.24.11/dpdk/pmd/rte_cr= yptodev.html#initialization

Thanks for offering a sync up - this would be ideal as we are still st= uck. We can schedule a Zoom and invite you. Do I remember correctly that yo= u are in the pacific time zone? Is any particular day this week good for yo= u?=C2=A0

Thanks for all the help.
-Patrick

On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah <hshah@marvell.com&g= t; wrote:
Hi Cody,=C2=A0

Can you please refer our SDK document? It should have clear instructions. W= e can sync up if you still have any questions.=C2=A0

Regards,
Hiral
From: Cody Cheng <ccheng@iol.unh.edu>
Sent: Friday, December 13, 2024 11:47 AM
To: Gnanesh Kambalu Palanethra <gpalanethra@marvell.com>; Hiral Shah <= ;hshah@marvell.com>
Cc: JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>= ;; Patrick Robb <= probb@iol.unh.edu>; ci@dpdk.org <ci@dpdk.org>
Subject: [EXTERNAL] CN10K Crypto Test Issue
=C2=A0
Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the Univ= ersity of New Hampshire DPDK Community Test Lab. We are hosting a CN10K boa= rd here which is currently running some ethernet device tests on DPDK, and = we would like to extend
H=
i Gnanesh & Hiral,

My name is Cody Cheng, I'm a tester at the University of New Hampshire
DPDK Community Test Lab. We are hosting a CN10K board here which is
currently running some ethernet device tests on DPDK, and we would
like to extend our testing to include crypto device testing. Gnanesh
has written a patch which adds testcases to the DPDK Test Suite which
should allow us to do so.

However, I am running into difficulties with the crypto devices I
create in DPDK from the CN10K board. I would appreciate it if I can
sync with one of you next week so that I can show our current
configuration, and run through the DPDK crypto device setup process
and CN10K autotest (not passing currently). I am guessing there is
some error in our configuration. My coworker Patrick Robb has
mentioned he met with Hiral previously and it was a big help for
understanding how to flash the correct firmware, build the SDK and
tftpboot it, chroot to Ubuntu etc. I hope we can do something similar
to clear up the confusion regarding crypto devs. What timezones are
you in? I would be happy to schedule a Zoom call.

Otherwise, I will share some of the system info and the process I have
run through below, which might begin to give you an idea regarding our
status:

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Marvell CN10k Boot Stub
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Firmware Version: 2024-12-07 02:04:42
EBF Version: 12.24.11, Branch:
/MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-external-f=
w-SDK12.24.11/firmware/ebf,
Built: Sat, 07 Dec 2024 02:02:27 +0000

Board Model:    crb106
Board Revision: r1p1
Board Serial:   <redacted>

Chip:  0xb9 Pass A1
SKU:   MV-CN10624-A1-AAP
LLC:   49152 KB
Boot:  SPI1_CS0,EMMC_CS0, using SPI1_CS0
AVS:   Enabled

I am setting up 1 crypto virtual function using the commands here:
=
https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guides_=
cryptodevs_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOy=
Paz7xtfQ&r=3DvGy6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwg=
TF6BzuBPsPbKfZfmAua-foxlSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFS=
GcAGResAexjf_pFNDJ0Szm68pM2tw5BFzUM&e=3D

So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1

At this stage, according to the docs I should be able to launch
dpdk-test and run the cn10k symmetrical crypto autotest, using the
commands below:

```
./dpdk-test
RTE>>cryptodev_cn10k_autotest
```

However, the auto tests fail and fall into an error loop which I have
attached the logs of in this email.

Here is the EAL output from the logs:

EAL: Detected CPU lcores: 24
EAL: Detected NUMA nodes: 1
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM)
CRYPTODEV: Creating cryptodev 0002:20:00.1
CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id:
0, max queue pairs: 0
APP: HPET is not enabled, using TSC as default timer

In the EAL output, max queue pairs is 0 even though in the docs, it
says the Maximum queue pairs limit is set to a default of 63. Could
this be related to the issue?

Also, here is my kernel cmdline parameters:

console=3DttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24
rootwait root=3D/dev/nvme0n1p1 rw coherent_pool=3D16M
default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8

Does this look correct?

I have also tried setting `iommu.passthrough=3D1` in the boot arguments
but that resulted in the same dpdk-test failure.

Best Regards,
Cody Cheng
--000000000000eeccd60629900b3d--