From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <ci-bounces@dpdk.org> Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F86E46536; Tue, 8 Apr 2025 19:07:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DE30140267; Tue, 8 Apr 2025 19:07:04 +0200 (CEST) Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by mails.dpdk.org (Postfix) with ESMTP id 9C74440264 for <ci@dpdk.org>; Tue, 8 Apr 2025 19:07:03 +0200 (CEST) Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-2ff69365e1dso4656993a91.3 for <ci@dpdk.org>; Tue, 08 Apr 2025 10:07:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1744132022; x=1744736822; darn=dpdk.org; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=FHxtelXoJdp4z6yLr5BKvsjfYJYvNfYdWgJ61h7wdNE=; b=h4+1e8biXYnS/3rtgs0lpQXHq0u9PL5EH58hHf+WfFNvdU9FSG2cr4M+Xljhq3yG0W 0yfhYbBGQWueWo60oa7BD7XCzWHv6ri7hly92x6L+7sVyEtW+L5iNDNX4eSmEU8P4+jT q6A1+dgbtyugYw3aZUOBqUbGe6GPBMYvlEfmw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744132022; x=1744736822; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=FHxtelXoJdp4z6yLr5BKvsjfYJYvNfYdWgJ61h7wdNE=; b=ZjSWRkVpOYo1rBFrdZ+crd5Yb232LVn6fMLVDL1xv+XBTCSVMYMC5p+CIzfFmIDEfr T2Q9FltvDYR5LyhSgGzF1LGJAsQZYxl19AkSX0wZXf8Yc6mEh0qTPLPfSO7DtI47BEUe hS+kBd2cpRTcH+FI6+pgTGwdpip8G737cjWk0jD1c8XdcW+x9ovotkzdCILFouNG6Lds uu4VFMBXilV42drs2JSze02affQATitnUrVXsrTcaXTvstLQ5SZQx1VyEbWLls1mPKiD RTN5TmRBrEwXNHviXPjU1zDq+vqFTmMSotlmA18CfNvrMOINdkO03EhLa5+bFpEV5mj3 X3ow== X-Forwarded-Encrypted: i=1; AJvYcCXGxXfJMls2tfxo6JM83dcbh3qIoJ7K7Ij88t41LJsTM3Zp+Jv2e4cuFOvB4Bdll08Ylw==@dpdk.org X-Gm-Message-State: AOJu0Yxclc75ERbgd6YS1b7bHR67gA7A2GTfWox4D359H2N2UwhHzXSa qhl2rZjq4bmZ3bGomsIMNunYK0VeLgK384goMGmzcrjhHKwlYwZgk1tSZ3D5KtepyJwBVBERrMR ZgMx12m7dLFY0s4MGY5Ls0mAEpfwRaIolzLG3cQ== X-Gm-Gg: ASbGnctJLDbdvLLrUEEBoIvNAxqtVNellOyXbGb5MdYYcbfyslSM7gWTD0zx0tqHFBo ozCwbtcWhe0NfhnPSU/BDBfjrUz6g0MZPjoM4BUKid4NspxsO3lpDPse/UUy05RAbG3H/iwC0Ja iXm8soQbe4H6+LwmIkeir0Q2S6dGw7+H3xDpKPGA55 X-Google-Smtp-Source: AGHT+IHKEhs4OB0QR7RjqWkxu4sw2ZTXoqYr2EU552dxYo0+ijOGfJ0iVmcQt+qwIpQQLyQcYwTM7TIZU3REsegT5G0= X-Received: by 2002:a17:90b:2747:b0:306:b6f7:58ba with SMTP id 98e67ed59e1d1-306dbb96599mr12629a91.6.1744132022547; Tue, 08 Apr 2025 10:07:02 -0700 (PDT) MIME-Version: 1.0 From: Patrick Robb <probb@iol.unh.edu> Date: Tue, 8 Apr 2025 13:02:56 -0400 X-Gm-Features: ATxdqUGs8g0yZ-VkaGDELwwom-DgMJpNE4O3MOVO6so-USapsWAGaOiHSbpgLvw Message-ID: <CAJvnSUC7UTYJD6jdddOV2AYxQfGsW-ZwC7FpPHJQUj+gv9rpXA@mail.gmail.com> Subject: Intel QuickAssist crypto operations testing To: Bruce Richardson <bruce.richardson@intel.com> Cc: Cody Cheng <ccheng@iol.unh.edu>, Dean Marx <dmarx@iol.unh.edu>, Adam Hassick <ahassick@iol.unh.edu>, Nicholas Pratte <npratte@iol.unh.edu>, ci@dpdk.org Content-Type: multipart/alternative; boundary="000000000000a55238063247616e" X-BeenThere: ci@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK CI discussions <ci.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/ci>, <mailto:ci-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/ci/> List-Post: <mailto:ci@dpdk.org> List-Help: <mailto:ci-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/ci>, <mailto:ci-request@dpdk.org?subject=subscribe> Errors-To: ci-bounces@dpdk.org --000000000000a55238063247616e Content-Type: text/plain; charset="UTF-8" Hi Bruce, Do you remember last year when we had a tech board call about the server refresh at UNH-IOL, you recommended that for the Intel processor DUT system, we get a processor SKU which includes a QAT device? We did this, and the SKU we selected was Intel(R) Xeon(R) Gold 5415+. Those devices are QAT 4xxx series QAT 4942 as reported by dpdk-devbind.py --status: Crypto devices using kernel driver ================================== 0000:76:00.0 '4xxx Series QAT 4942' numa_node=0 drv=4xxx unused=qat_4xxx,vfio-pci 0000:f3:00.0 '4xxx Series QAT 4942' numa_node=1 drv=4xxx unused=qat_4xxx,vfio-pci Cody has been setting up the testing for this QAT device, which is done via DPDK's test-crypto-perf application. He is satisfied with the metrics the card is getting with DPDK (he compared them against some reports Intel has published and also what we see on a QAT PCI card on an Ampere ARM system here at UNH). So, he thinks we are ready to go online. However, in order to be careful, we were wondering if we should run the information we have by an Intel contact first. Is there any DPDK/quickassist/crypto person on your team who could serve as a contact for this purpose? If so, I think Cody can add them to this thread and share the more detailed info for that person for them to approve (or disapprove). Thanks let me know! -Patrick --000000000000a55238063247616e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable <div dir=3D"ltr"><div>Hi Bruce,</div><div><br></div><div>Do you remember la= st year when we had a tech board call about the server refresh at UNH-IOL, = you recommended that for the Intel processor DUT system, we get a processor= SKU which includes a QAT device? We did this, and the SKU we selected was = Intel(R) Xeon(R) Gold 5415+.</div><div><br></div><div>Those devices are QAT= 4xxx series QAT 4942 as reported by dpdk-devbind.py --status:</div><div><b= r></div><div>Crypto devices using kernel driver<br>=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D<br>0000:76:00.0 '4xxx Series QAT 4942' numa_node=3D0 drv=3D4xxx= unused=3Dqat_4xxx,vfio-pci <br>0000:f3:00.0 '4xxx Series QAT 4942'= numa_node=3D1 drv=3D4xxx unused=3Dqat_4xxx,vfio-pci</div><div><br></div><d= iv>Cody has been setting up the testing for this QAT device, which is done = via DPDK's=C2=A0test-crypto-perf application. He is satisfied with the = metrics the card is getting with DPDK (he compared them against some report= s Intel has published and also what we=C2=A0see on a QAT PCI card on an Amp= ere ARM system here at UNH).=C2=A0</div><div><br></div><div>So, he thinks w= e are ready to go online. However, in order to be careful, we were wonderin= g if we should run the information we have by an Intel contact first. Is th= ere any DPDK/quickassist/crypto person on your team who could serve as a co= ntact for this purpose? If so, I think Cody can add them to this thread and= share the more detailed info for that person for them to approve (or disap= prove).=C2=A0</div><div><br></div><div>Thanks let me know!</div><div><br></= div><div>-Patrick</div><div><br></div><div><br></div></div> --000000000000a55238063247616e--