[dpdk-dev] [PATCH 0/2] Fix parameters and prefetch function on IBM POWER8

[dpdk-dev] [PATCH 0/2] Fix parameters and prefetch function on IBM POWER8

[Chao Zhu]

This patch set fixes CPU/memory parameters and correct wrong prefetch settings for IBM POWER8.

Chao Zhu (2):
  Fix CPU and memory parameters on IBM POWER8
  Fix prefetch instruction on IBM POWER8

 config/common_base                                 |    3 ++-
 lib/librte_eal/common/eal_common_options.c         |    2 +-
 .../common/include/arch/ppc_64/rte_prefetch.h      |    6 +++---
 3 files changed, 6 insertions(+), 5 deletions(-)

[dpdk-dev] [PATCH 1/2] Fix CPU and memory parameters on IBM POWER8

[Chao Zhu]

This patch fixes the max logic number and memory channel number settings
on IBM POWER8 platform.
1. The max number of logic cores of a POWER8 processor is 96. Normally,
   there are two sockets on a server. So the max number of logic cores
   are 192. So this parch set CONFIG_RTE_MAX_LCORE to 256.
2. Currently, the max number of memory channels are hardcoded to 4. However,
   on a POWER8 machine, the max number of memory channels are 8. To fix this,
   CONFIG_RTE_MAX_NCHANNELS is added to do the configuration.

Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
---
 config/common_base                         |    3 ++-
 lib/librte_eal/common/eal_common_options.c |    2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/config/common_base b/config/common_base
index dbd405b..1beea32 100644
--- a/config/common_base
+++ b/config/common_base
@@ -83,10 +83,11 @@ CONFIG_RTE_CACHE_LINE_SIZE=64
 # Compile Environment Abstraction Layer
 #
 CONFIG_RTE_LIBRTE_EAL=y
-CONFIG_RTE_MAX_LCORE=128
+CONFIG_RTE_MAX_LCORE=256
 CONFIG_RTE_MAX_NUMA_NODES=8
 CONFIG_RTE_MAX_MEMSEG=256
 CONFIG_RTE_MAX_MEMZONE=2560
+CONFIG_RTE_MAX_NCHANNELS=8
 CONFIG_RTE_MAX_TAILQ=32
 CONFIG_RTE_LOG_LEVEL=8
 CONFIG_RTE_LOG_HISTORY=256
diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c
index 29942ea..6c268c1 100644
--- a/lib/librte_eal/common/eal_common_options.c
+++ b/lib/librte_eal/common/eal_common_options.c
@@ -798,7 +798,7 @@ eal_parse_common_option(int opt, const char *optarg,
 	case 'n':
 		conf->force_nchannel = atoi(optarg);
 		if (conf->force_nchannel == 0 ||
-		    conf->force_nchannel > 4) {
+		    conf->force_nchannel > RTE_MAX_NCHANNELS) {
 			RTE_LOG(ERR, EAL, "invalid channel number\n");
 			return -1;
 		}
-- 
1.7.1

Re: [dpdk-dev] [PATCH 1/2] Fix CPU and memory parameters on IBM POWER8

[David Marchand]

On Fri, Mar 25, 2016 at 9:11 AM, Chao Zhu <chaozhu@linux.vnet.ibm.com> wrote:
> This patch fixes the max logic number and memory channel number settings
> on IBM POWER8 platform.
> 1. The max number of logic cores of a POWER8 processor is 96. Normally,
>    there are two sockets on a server. So the max number of logic cores
>    are 192. So this parch set CONFIG_RTE_MAX_LCORE to 256.

This is a power8 configuration item, this should go to power8 config
file, not common_base.

> 2. Currently, the max number of memory channels are hardcoded to 4. However,
>    on a POWER8 machine, the max number of memory channels are 8. To fix this,
>    CONFIG_RTE_MAX_NCHANNELS is added to do the configuration.

I don't see any reason why we would need a max value for force_nchannel.
We should just get rid of this check, this is an obscure parameter for
most people, so people playing with it know what they are doing
(hopefully ?).

On the other hand, if power8 has some specifics about it, maybe we
should introduce some default value in a arch eal header for other
dpdk components to use (like in mempool).
Thoughts ?


-- 
David Marchand

Re: [dpdk-dev] [PATCH 1/2] Fix CPU and memory parameters on IBM POWER8

[Thomas Monjalon]

2016-03-25 09:48, David Marchand:
> On Fri, Mar 25, 2016 at 9:11 AM, Chao Zhu <chaozhu@linux.vnet.ibm.com> wrote:
> > This patch fixes the max logic number and memory channel number settings
> > on IBM POWER8 platform.
> > 1. The max number of logic cores of a POWER8 processor is 96. Normally,
> >    there are two sockets on a server. So the max number of logic cores
> >    are 192. So this parch set CONFIG_RTE_MAX_LCORE to 256.
> 
> This is a power8 configuration item, this should go to power8 config
> file, not common_base.
> 
> > 2. Currently, the max number of memory channels are hardcoded to 4. However,
> >    on a POWER8 machine, the max number of memory channels are 8. To fix this,
> >    CONFIG_RTE_MAX_NCHANNELS is added to do the configuration.
> 
> I don't see any reason why we would need a max value for force_nchannel.
> We should just get rid of this check, this is an obscure parameter for
> most people, so people playing with it know what they are doing
> (hopefully ?).
> 
> On the other hand, if power8 has some specifics about it, maybe we
> should introduce some default value in a arch eal header for other
> dpdk components to use (like in mempool).
> Thoughts ?

Chao? We are running out of time for 16.04.

Re: [dpdk-dev] [PATCH 1/2] Fix CPU and memory parameters on IBM POWER8

[Chao Zhu]

Thomas,

Seems I didn't get the messages from David. Anyway, I sent out an updated
patch.
Thanks for reminder!

-----Original Message-----
From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] 
Sent: 2016年3月30日 18:53
To: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Cc: dev@dpdk.org; David Marchand <david.marchand@6wind.com>; Richardson,
Bruce <bruce.richardson@intel.com>; Panu Matilainen <pmatilai@redhat.com>
Subject: Re: [dpdk-dev] [PATCH 1/2] Fix CPU and memory parameters on IBM
POWER8

2016-03-25 09:48, David Marchand:
> On Fri, Mar 25, 2016 at 9:11 AM, Chao Zhu <chaozhu@linux.vnet.ibm.com>
wrote:
> > This patch fixes the max logic number and memory channel number 
> > settings on IBM POWER8 platform.
> > 1. The max number of logic cores of a POWER8 processor is 96. Normally,
> >    there are two sockets on a server. So the max number of logic cores
> >    are 192. So this parch set CONFIG_RTE_MAX_LCORE to 256.
> 
> This is a power8 configuration item, this should go to power8 config 
> file, not common_base.
> 
> > 2. Currently, the max number of memory channels are hardcoded to 4.
However,
> >    on a POWER8 machine, the max number of memory channels are 8. To fix
this,
> >    CONFIG_RTE_MAX_NCHANNELS is added to do the configuration.
> 
> I don't see any reason why we would need a max value for force_nchannel.
> We should just get rid of this check, this is an obscure parameter for 
> most people, so people playing with it know what they are doing 
> (hopefully ?).
> 
> On the other hand, if power8 has some specifics about it, maybe we 
> should introduce some default value in a arch eal header for other 
> dpdk components to use (like in mempool).
> Thoughts ?

Chao? We are running out of time for 16.04.

[dpdk-dev] [PATCH 2/2] Fix prefetch instruction on IBM POWER8

[Chao Zhu]

Current prefetch instruction (dcbt) implementation for IBM POWER8 has wrong
Touch Hint(TH) parameter. The current setting of TH=1 indicates to load data from
current cache line and an unlimited number of sequentially following cache lines.
TTH=0 means to load data from current cache line. rte_prefetch0 function is defined
to load one cache line, which means TH=0 is suited here.

Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
---
 .../common/include/arch/ppc_64/rte_prefetch.h      |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h
index bcc7185..9a1995e 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h
@@ -41,17 +41,17 @@ extern "C" {
 
 static inline void rte_prefetch0(const volatile void *p)
 {
-	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+	asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
 }
 
 static inline void rte_prefetch1(const volatile void *p)
 {
-	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+	asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
 }
 
 static inline void rte_prefetch2(const volatile void *p)
 {
-	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+	asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
 }
 
 static inline void rte_prefetch_non_temporal(const volatile void *p)
-- 
1.7.1