From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [125.16.236.2]) by dpdk.org (Postfix) with ESMTP id 0750D68F2 for ; Thu, 19 May 2016 11:13:04 +0200 (CEST) Received: from localhost by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 19 May 2016 14:43:03 +0530 Received: from d28dlp03.in.ibm.com (9.184.220.128) by e28smtp02.in.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Thu, 19 May 2016 14:42:57 +0530 X-IBM-Helo: d28dlp03.in.ibm.com X-IBM-MailFrom: chaozhu@linux.vnet.ibm.com X-IBM-RcptTo: dev@dpdk.org Received: from d28relay02.in.ibm.com (d28relay02.in.ibm.com [9.184.220.59]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 5D401125805B for ; Thu, 19 May 2016 14:45:10 +0530 (IST) Received: from d28av03.in.ibm.com (d28av03.in.ibm.com [9.184.220.65]) by d28relay02.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u4J9CrcE17563848 for ; Thu, 19 May 2016 14:42:53 +0530 Received: from d28av03.in.ibm.com (localhost [127.0.0.1]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u4J9CtCs010226 for ; Thu, 19 May 2016 14:42:55 +0530 Received: from ADMINIB2M8Q79C ([9.186.50.151]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u4J9Cmul008881; Thu, 19 May 2016 14:42:50 +0530 From: "Chao Zhu" To: "'Olivier Matz'" , Cc: , , References: <1463143859-3105-1-git-send-email-olivier.matz@6wind.com> <1463479192-2488-1-git-send-email-olivier.matz@6wind.com> <1463479192-2488-7-git-send-email-olivier.matz@6wind.com> In-Reply-To: <1463479192-2488-7-git-send-email-olivier.matz@6wind.com> Date: Thu, 19 May 2016 17:13:52 +0800 Message-ID: <000301d1b1ae$cebf1470$6c3d3d50$@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 15.0 Thread-Index: AQFvWQjkTuva4JuuLgj8jHfVWgXtHAE87zmKArbVcbWgZQwuMA== Content-Language: zh-cn X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16051909-0005-0000-0000-00000CF43C3A X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused Subject: Re: [dpdk-dev] [PATCH v2 6/7] virtio: fix pci accesses for ppc64 in legacy mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 May 2016 09:13:05 -0000 Olivier, Thanks for the patches!=20 Just one comment: POWER8 machine only supports little endian OS on bare metal. In VM = guest, it can support both little endian and big endian OS. Did you try to run it = on both host (little endian) and guest (big endian and little endian)? -----Original Message----- From: Olivier Matz [mailto:olivier.matz@6wind.com]=20 Sent: 2016=C4=EA5=D4=C217=C8=D5 18:00 To: dev@dpdk.org Cc: david.marchand@6wind.com; chaozhu@linux.vnet.ibm.com; = yuanhan.liu@linux. intel.com; huawei.xie@intel.com Subject: [PATCH v2 6/7] virtio: fix pci accesses for ppc64 in legacy = mode From: David Marchand Although ppc supports both endianesses, qemu supposes that the cpu is = big endian and enforces this for the virtio-net stuff. Fix PCI accesses in legacy mode. Only ppc64le is supported at the = moment. Signed-off-by: David Marchand Signed-off-by: Olivier Matz --- drivers/net/virtio/virtio_pci.c | 68 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c index 9cdca06..ebf4cf7 100644 --- a/drivers/net/virtio/virtio_pci.c +++ b/drivers/net/virtio/virtio_pci.c @@ -55,20 +55,88 @@ */ #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20) +/* + * Since we are in legacy mode: + * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf + * + * "Note that this is possible because while the virtio header is PCI = (i.e. + * little) endian, the device-specific region is encoded in the native=20 +endian of + * the guest (where such distinction is applicable)." + * + * For powerpc which supports both, qemu supposes that cpu is big=20 +endian and + * enforces this for the virtio-net stuff. + */ + static void legacy_read_dev_config(struct virtio_hw *hw, size_t offset, void *dst, int length) { +#ifdef RTE_ARCH_PPC_64 + int size; + + while (length > 0) { + if (length >=3D 4) { + size =3D 4; + rte_eal_pci_ioport_read(&hw->io, dst, size, + VIRTIO_PCI_CONFIG(hw) + offset); + *(uint32_t *)dst =3D rte_be_to_cpu_32(*(uint32_t *)dst); + } else if (length >=3D 2) { + size =3D 2; + rte_eal_pci_ioport_read(&hw->io, dst, size, + VIRTIO_PCI_CONFIG(hw) + offset); + *(uint16_t *)dst =3D rte_be_to_cpu_16(*(uint16_t *)dst); + } else { + size =3D 1; + rte_eal_pci_ioport_read(&hw->io, dst, size, + VIRTIO_PCI_CONFIG(hw) + offset); + } + + dst =3D (char *)dst + size; + offset +=3D size; + length -=3D size; + } +#else rte_eal_pci_ioport_read(&hw->io, dst, length, VIRTIO_PCI_CONFIG(hw) + offset); +#endif } static void legacy_write_dev_config(struct virtio_hw *hw, size_t offset, const void *src, int length) { +#ifdef RTE_ARCH_PPC_64 + union { + uint32_t u32; + uint16_t u16; + } tmp; + int size; + + while (length > 0) { + if (length >=3D 4) { + size =3D 4; + tmp.u32 =3D rte_cpu_to_be_32(*(const uint32_t *)src); + rte_eal_pci_ioport_write(&hw->io, &tmp.u32, size, + VIRTIO_PCI_CONFIG(hw) + offset); + } else if (length >=3D 2) { + size =3D 2; + tmp.u16 =3D rte_cpu_to_be_16(*(const uint16_t *)src); + rte_eal_pci_ioport_write(&hw->io, &tmp.u16, size, + VIRTIO_PCI_CONFIG(hw) + offset); + } else { + size =3D 1; + rte_eal_pci_ioport_write(&hw->io, src, size, + VIRTIO_PCI_CONFIG(hw) + offset); + } + + src =3D (const char *)src + size; + offset +=3D size; + length -=3D size; + } +#else rte_eal_pci_ioport_write(&hw->io, src, length, VIRTIO_PCI_CONFIG(hw) + offset); +#endif } static uint64_t -- 2.8.0.rc3