From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7014A0524; Thu, 6 May 2021 05:33:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A2BD7410EE; Thu, 6 May 2021 05:33:30 +0200 (CEST) Received: from smtpproxy21.qq.com (smtpbg702.qq.com [203.205.195.102]) by mails.dpdk.org (Postfix) with ESMTP id CCD25410EE for ; Thu, 6 May 2021 05:33:28 +0200 (CEST) X-QQ-mid: bizesmtp50t1620271998tyojo2dp Received: from jiawenwu (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Thu, 06 May 2021 11:33:17 +0800 (CST) X-QQ-SSF: 01400000002000D0E000B00A0000000 X-QQ-FEAT: wZTf/GsjKWAQ11l/NdlvNVQ887ePPBo/bmu61mj/nn9nxlQYPxp/5Wr33x1Lt 6QTZGz9xByST7Gx/QSkDwQXW72PJPyfT+RkWHfbVmXG/iel05T0q4rMf7pLC6EdwGmUGPf0 ijdeWC9JTszLico7A54hXkw8MHhxVLrDGcapGe1RVJTImsNkPvpZCA+fntxmBfOjem2QagO IA1YQuvVq+DCIVTMhnOkCDTtrCCfULKMe5aDXtM99UUw9bPhDdGKi0eUyHFYhKRkjbv1Rmj oyqbJIAsuKtAsVxar1aozOHW8YY0SBXRwlxsDRzeTeIqRT0DDg9AfMF0UeWuedbHH6UmDrw IJXIo28SwjyaxdhdDI= X-QQ-GoodBg: 2 From: "Jiawen Wu" To: "'Ferruh Yigit'" , Cc: References: <20210429103335.23060-1-jiawenwu@trustnetic.com> <20210429103335.23060-2-jiawenwu@trustnetic.com> <1fd58ff8-5028-2216-eec7-1437630de896@intel.com> In-Reply-To: <1fd58ff8-5028-2216-eec7-1437630de896@intel.com> Date: Thu, 6 May 2021 11:33:17 +0800 Message-ID: <002601d74228$8dfc5b90$a9f512b0$@trustnetic.com>+9F0185DE8780972F MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Content-Language: zh-cn Thread-Index: AQJHgyLWsk1k8Vlpl8OBLLWX+ze9ZQGsiAioAmh0AfOp1JS5EA== X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign6 X-QQ-Bgrelay: 1 Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v2 1/5] net/txgbe: fix RSS in QINQ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On April 29, 2021 10:31 PM, Ferruh Yigit wrote: > On 4/29/2021 11:33 AM, Jiawen Wu wrote: > > Support to enable and disable QINQ hardware strip, when configure = vlan > > offload with QINQ strip mask, to avoid RSS does not work for QINQ > > packets. > > >=20 > Hi Jiawen, >=20 > What was not working and fixed here? > Is it RSS hash calculation is wrong when packet has double VLAN tag? = Is it > failing to calculate hash for VLAN field of the packet or calculation = for any fields > are wrong? Can't device detect/parse QinQ fields? >=20 > And how enabling QinQ strip is solving the issue? Should user enable = QinQ strip > before configuring the RSS? What happens if user don't, should driver = has > checks to cover this, like fail to enable RSS if QinQ strip is not = enable etc? >=20 > Can you please provide more details? >=20 Hi Ferruh, I think I might be mistaken something. At first I fixed this bug because RSS did not take effect when packet = has QINQ tag. Hardware does not support to calculate VLAN field, but the insertion of = QINQ causes five-tuple filed changes. The root cause is that QINQ is not properly stripped. So I add the = functions to handle QINQ stripping when ETH_QINQ_STRIP_MASK set. And users should enable QINQ strip before configuring the RSS. This patch should be renamed to "fix to strip QINQ", is this more = appropriate? >=20 > > Fixes: 220b0e49bc47 ("net/txgbe: support VLAN") > > Cc: stable@dpdk.org > > > > Signed-off-by: Jiawen Wu > > --- > > drivers/net/txgbe/txgbe_ethdev.c | 39 > > +++++++++++++++++++++++++++----- > > 1 file changed, 33 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/net/txgbe/txgbe_ethdev.c > > b/drivers/net/txgbe/txgbe_ethdev.c > > index 97796f040b..3d6d356102 100644 > > --- a/drivers/net/txgbe/txgbe_ethdev.c > > +++ b/drivers/net/txgbe/txgbe_ethdev.c > > @@ -1209,7 +1209,6 @@ txgbe_vlan_hw_extend_disable(struct > rte_eth_dev > > *dev) > > > > ctrl =3D rd32(hw, TXGBE_PORTCTL); > > ctrl &=3D ~TXGBE_PORTCTL_VLANEXT; > > - ctrl &=3D ~TXGBE_PORTCTL_QINQ; > > wr32(hw, TXGBE_PORTCTL, ctrl); > > } > > > > @@ -1217,17 +1216,38 @@ static void > > txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) { > > struct txgbe_hw *hw =3D TXGBE_DEV_HW(dev); > > - struct rte_eth_rxmode *rxmode =3D &dev->data->dev_conf.rxmode; > > - struct rte_eth_txmode *txmode =3D &dev->data->dev_conf.txmode; > > uint32_t ctrl; > > > > PMD_INIT_FUNC_TRACE(); > > > > ctrl =3D rd32(hw, TXGBE_PORTCTL); > > ctrl |=3D TXGBE_PORTCTL_VLANEXT; > > - if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP || > > - txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT) > > - ctrl |=3D TXGBE_PORTCTL_QINQ; > > + wr32(hw, TXGBE_PORTCTL, ctrl); > > +} > > + > > +static void > > +txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev) { > > + struct txgbe_hw *hw =3D TXGBE_DEV_HW(dev); > > + uint32_t ctrl; > > + > > + PMD_INIT_FUNC_TRACE(); > > + > > + ctrl =3D rd32(hw, TXGBE_PORTCTL); > > + ctrl &=3D ~TXGBE_PORTCTL_QINQ; > > + wr32(hw, TXGBE_PORTCTL, ctrl); > > +} > > + > > +static void > > +txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev) { > > + struct txgbe_hw *hw =3D TXGBE_DEV_HW(dev); > > + uint32_t ctrl; > > + > > + PMD_INIT_FUNC_TRACE(); > > + > > + ctrl =3D rd32(hw, TXGBE_PORTCTL); > > + ctrl |=3D TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT; > > wr32(hw, TXGBE_PORTCTL, ctrl); > > } > > > > @@ -1294,6 +1314,13 @@ txgbe_vlan_offload_config(struct rte_eth_dev > *dev, int mask) > > txgbe_vlan_hw_extend_disable(dev); > > } > > > > + if (mask & ETH_QINQ_STRIP_MASK) { > > + if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP) > > + txgbe_qinq_hw_strip_enable(dev); > > + else > > + txgbe_qinq_hw_strip_disable(dev); > > + } > > + > > return 0; > > } > > > >