From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 158ADA00C3; Wed, 22 Jun 2022 04:44:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F35714069F; Wed, 22 Jun 2022 04:44:17 +0200 (CEST) Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by mails.dpdk.org (Postfix) with ESMTP id 8FE514069F for ; Wed, 22 Jun 2022 04:44:16 +0200 (CEST) X-QQ-mid: bizesmtp80t1655865849t4qekmim Received: from lapjiawenwu ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 10:44:08 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: Z953UCsBqO4r+cil0o/jlQheBU3F8C0Uto+J3Pbsn7wenV2DeMo+iyOliC9SS X2z01UstOUGJ+TMYWeAf9fYVHBGsqe1jHHl8YDRqvxfEoKx4ficOMEYPO9NSEKH2mldtRzu Vffv0o0om12FV/D0Z06enJlwlmy5PEhDu5zAjoTEx/2ft1kWS8aRBPA6Wq2I31LP8lQD+hK XnUkmmFwJt+QJh6gNZv3cqDRXGS9TLSs9Wk6bLK8bGSU+TLGMStNntG7TIu/QawAjuADPPO uaIJiPRIyM6Kzg0JyQVr5EWvAy0C7ODDW3+Pz/1+0Edaj4a/+ckmZiFQUiLqTLB90MigNcw TJDK1w1T5ykqsYIHYnVDUsUxLAZMg== X-QQ-GoodBg: 2 From: "Jiawen Wu" To: "'Ferruh Yigit'" Cc: , References: <20220620075512.588744-1-jiawenwu@trustnetic.com> <20220620075512.588744-4-jiawenwu@trustnetic.com> <8d89c0b2-f9cb-e3e5-72e1-736f655ab5c3@xilinx.com> In-Reply-To: <8d89c0b2-f9cb-e3e5-72e1-736f655ab5c3@xilinx.com> Subject: RE: [PATCH 3/7] net/txgbe: fix register polling Date: Wed, 22 Jun 2022 10:44:08 +0800 Message-ID: <00c401d885e1$f2b8c200$d82a4600$@trustnetic.com>+0E2B3E0ACDE22367 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQK89qVCPMWGRVHm0tw0gcCv40uU/QKPKxiMAcWrENGrbykV0A== Content-Language: zh-cn X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign8 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Tuesday, June 21, 2022 8:19 PM, Ferruh Yigit wrote: > On 6/20/2022 8:55 AM, Jiawen Wu wrote: > > Fix to poll some specific registers, which expect bit 0. > > > > Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers") > > Cc: stable@dpdk.org > > > > Signed-off-by: Jiawen Wu > > --- > > drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++--- > > 1 file changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/net/txgbe/base/txgbe_regs.h > > b/drivers/net/txgbe/base/txgbe_regs.h > > index 3139796911..911bb6e04e 100644 > > --- a/drivers/net/txgbe/base/txgbe_regs.h > > +++ b/drivers/net/txgbe/base/txgbe_regs.h > > @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, > u32 expect, u32 *actual, > > } > > > > do { > > - all |=3D rd32(hw, reg); > > - value |=3D mask & all; > > + if (expect !=3D 0) { > > + all |=3D rd32(hw, reg); > > + value |=3D mask & all; > > + } else { > > + all =3D rd32(hw, reg); > > + value =3D mask & all; > > + } > > if (value =3D=3D expect) > > break; > > > > @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, > > u32 expect, u32 *actual, > > > > #define wr32w(hw, reg, val, mask, slice) do { \ > > wr32((hw), reg, val); \ > > - po32m((hw), reg, mask, mask, NULL, 5, slice); \ > > + po32m((hw), reg, mask, 0, NULL, 5, slice); \ >=20 > Just to double check, is this change intentional, to always expect = reading '0' > from registers after writing to them? >=20 > Perhaps you can explain a little more about this polling after = read/write logic > and what was wrong in the commit log. >=20 This is exactly what register expects. 'wr32w' is used for IPsec Rx = Index register. For this register, when write command bit set, the content of register = affected, and immediately self cleared by hardware. So it always expect reading '0' from register mask = 'TXGBE_IPSRXIDX_WRITE'. > > } while (0) > > > > #define TXGBE_XPCS_IDAADDR 0x13000