From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7E11A04C5; Fri, 4 Sep 2020 12:34:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 390BA1C0CE; Fri, 4 Sep 2020 12:34:23 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 6E2F01C0C2 for ; Fri, 4 Sep 2020 12:34:21 +0200 (CEST) IronPort-SDR: NyNed92JGg24kbHyjIB0brGm5hIpUeufZsD2fvHw7vsPj2fLQNpWrZUp9mnzFN4w81hoLmpTdn ID3YPp7BMEPg== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="137242229" X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="137242229" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2020 03:34:20 -0700 IronPort-SDR: Turxqt3FZgFkikLjdZGODutramu4/p14Mp7jJTpobVRdKS4vWc1R3gWeXB3VtrkvO8Nxtt5yC+ S2ZxK0KmWE9Q== X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="478440734" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.251.81.88]) ([10.251.81.88]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2020 03:34:16 -0700 To: "Wei Hu (Xavier)" , dev@dpdk.org Cc: xavier.huwei@huawei.com References: <20200825115305.58490-1-huwei013@chinasoftinc.com> <20200825115305.58490-6-huwei013@chinasoftinc.com> From: Ferruh Yigit Autocrypt: addr=ferruh.yigit@intel.com; prefer-encrypt=mutual; keydata= mQINBFXZCFABEADCujshBOAaqPZpwShdkzkyGpJ15lmxiSr3jVMqOtQS/sB3FYLT0/d3+bvy qbL9YnlbPyRvZfnP3pXiKwkRoR1RJwEo2BOf6hxdzTmLRtGtwWzI9MwrUPj6n/ldiD58VAGQ +iR1I/z9UBUN/ZMksElA2D7Jgg7vZ78iKwNnd+vLBD6I61kVrZ45Vjo3r+pPOByUBXOUlxp9 GWEKKIrJ4eogqkVNSixN16VYK7xR+5OUkBYUO+sE6etSxCr7BahMPKxH+XPlZZjKrxciaWQb +dElz3Ab4Opl+ZT/bK2huX+W+NJBEBVzjTkhjSTjcyRdxvS1gwWRuXqAml/sh+KQjPV1PPHF YK5LcqLkle+OKTCa82OvUb7cr+ALxATIZXQkgmn+zFT8UzSS3aiBBohg3BtbTIWy51jNlYdy ezUZ4UxKSsFuUTPt+JjHQBvF7WKbmNGS3fCid5Iag4tWOfZoqiCNzxApkVugltxoc6rG2TyX CmI2rP0mQ0GOsGXA3+3c1MCdQFzdIn/5tLBZyKy4F54UFo35eOX8/g7OaE+xrgY/4bZjpxC1 1pd66AAtKb3aNXpHvIfkVV6NYloo52H+FUE5ZDPNCGD0/btFGPWmWRmkPybzColTy7fmPaGz cBcEEqHK4T0aY4UJmE7Ylvg255Kz7s6wGZe6IR3N0cKNv++O7QARAQABtCVGZXJydWggWWln aXQgPGZlcnJ1aC55aWdpdEBpbnRlbC5jb20+iQJsBBMBCgBWAhsDAh4BAheABQsJCAcDBRUK CQgLBRYCAwEABQkKqZZ8FiEE0jZTh0IuwoTjmYHH+TPrQ98TYR8FAl6ha3sXGHZrczovL2tl eXMub3BlbnBncC5vcmcACgkQ+TPrQ98TYR8uLA//QwltuFliUWe60xwmu9sY38c1DXvX67wk UryQ1WijVdIoj4H8cf/s2KtyIBjc89R254KMEfJDao/LrXqJ69KyGKXFhFPlF3VmFLsN4XiT PSfxkx8s6kHVaB3O183p4xAqnnl/ql8nJ5ph9HuwdL8CyO5/7dC/MjZ/mc4NGq5O9zk3YRGO lvdZAp5HW9VKW4iynvy7rl3tKyEqaAE62MbGyfJDH3C/nV/4+mPc8Av5rRH2hV+DBQourwuC ci6noiDP6GCNQqTh1FHYvXaN4GPMHD9DX6LtT8Fc5mL/V9i9kEVikPohlI0WJqhE+vQHFzR2 1q5nznE+pweYsBi3LXIMYpmha9oJh03dJOdKAEhkfBr6n8BWkWQMMiwfdzg20JX0o7a/iF8H 4dshBs+dXdIKzPfJhMjHxLDFNPNH8zRQkB02JceY9ESEah3wAbzTwz+e/9qQ5OyDTQjKkVOo cxC2U7CqeNt0JZi0tmuzIWrfxjAUulVhBmnceqyMOzGpSCQIkvalb6+eXsC9V1DZ4zsHZ2Mx Hi+7pCksdraXUhKdg5bOVCt8XFmx1MX4AoV3GWy6mZ4eMMvJN2hjXcrreQgG25BdCdcxKgqp e9cMbCtF+RZax8U6LkAWueJJ1QXrav1Jk5SnG8/5xANQoBQKGz+yFiWcgEs9Tpxth15o2v59 gXK5Ag0EV9ZMvgEQAKc0Db17xNqtSwEvmfp4tkddwW9XA0tWWKtY4KUdd/jijYqc3fDD54ES YpV8QWj0xK4YM0dLxnDU2IYxjEshSB1TqAatVWz9WtBYvzalsyTqMKP3w34FciuL7orXP4Ai bPtrHuIXWQOBECcVZTTOdZYGAzaYzxiAONzF9eTiwIqe9/oaOjTwTLnOarHt16QApTYQSnxD UQljeNvKYt1lZE/gAUUxNLWsYyTT+22/vU0GDUahsJxs1+f1yEr+OGrFiEAmqrzpF0lCS3f/ 3HVTU6rS9cK3glVUeaTF4+1SK5ZNO35piVQCwphmxa+dwTG/DvvHYCtgOZorTJ+OHfvCnSVj sM4kcXGjJPy3JZmUtyL9UxEbYlrffGPQI3gLXIGD5AN5XdAXFCjjaID/KR1c9RHd7Oaw0Pdc q9UtMLgM1vdX8RlDuMGPrj5sQrRVbgYHfVU/TQCk1C9KhzOwg4Ap2T3tE1umY/DqrXQgsgH7 1PXFucVjOyHMYXXugLT8YQ0gcBPHy9mZqw5mgOI5lCl6d4uCcUT0l/OEtPG/rA1lxz8ctdFB VOQOxCvwRG2QCgcJ/UTn5vlivul+cThi6ERPvjqjblLncQtRg8izj2qgmwQkvfj+h7Ex88bI 8iWtu5+I3K3LmNz/UxHBSWEmUnkg4fJlRr7oItHsZ0ia6wWQ8lQnABEBAAGJAjwEGAEKACYC GwwWIQTSNlOHQi7ChOOZgcf5M+tD3xNhHwUCXqFrngUJCKxSYAAKCRD5M+tD3xNhH3YWD/9b cUiWaHJasX+OpiuZ1Li5GG3m9aw4lR/k2lET0UPRer2Jy1JsL+uqzdkxGvPqzFTBXgx/6Byz EMa2mt6R9BCyR286s3lxVS5Bgr5JGB3EkpPcoJT3A7QOYMV95jBiiJTy78Qdzi5LrIu4tW6H o0MWUjpjdbR01cnj6EagKrDx9kAsqQTfvz4ff5JIFyKSKEHQMaz1YGHyCWhsTwqONhs0G7V2 0taQS1bGiaWND0dIBJ/u0pU998XZhmMzn765H+/MqXsyDXwoHv1rcaX/kcZIcN3sLUVcbdxA WHXOktGTQemQfEpCNuf2jeeJlp8sHmAQmV3dLS1R49h0q7hH4qOPEIvXjQebJGs5W7s2vxbA 5u5nLujmMkkfg1XHsds0u7Zdp2n200VC4GQf8vsUp6CSMgjedHeF9zKv1W4lYXpHp576ZV7T GgsEsvveAE1xvHnpV9d7ZehPuZfYlP4qgo2iutA1c0AXZLn5LPcDBgZ+KQZTzm05RU1gkx7n gL9CdTzVrYFy7Y5R+TrE9HFUnsaXaGsJwOB/emByGPQEKrupz8CZFi9pkqPuAPwjN6Wonokv ChAewHXPUadcJmCTj78Oeg9uXR6yjpxyFjx3vdijQIYgi5TEGpeTQBymLANOYxYWYOjXk+ae dYuOYKR9nbPv+2zK9pwwQ2NXbUBystaGyQ== Message-ID: <0123f152-4d76-424d-a482-376c989a0fcd@intel.com> Date: Fri, 4 Sep 2020 11:34:13 +0100 MIME-Version: 1.0 In-Reply-To: <20200825115305.58490-6-huwei013@chinasoftinc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH 05/11] net/hns3: add more hardware error types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 8/25/2020 12:52 PM, Wei Hu (Xavier) wrote: > From: "Wei Hu (Xavier)" > > The new firmware adds the hardware error types reported by MSI-x mode. > These errors are defined as RAS errors in hardware and belong to a > different type from the MSI-x errors processed by the driver. > > When hardware detects an hardware errors, which need to be handled with > the driver otherwise the device cannot run properly, it reports error > information through the MSI-x interrupt. After receiving the interrupt > reported by the hardware, the driver queries the error information and > identifies the error level, then rectifies the error. All errors will be > logged. In addition, the hardware may be reset at the function or global > level based on the error level. After the reset is complete, the hardware > will recovers to the normal status. > > Signed-off-by: Hongbo Zheng > Signed-off-by: Wei Hu (Xavier) <...> > + bd_num = RTE_MAX(mpf_bd_num, pf_bd_num); > desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0); > if (desc == NULL) { > - hns3_err(hw, "fail to zmalloc desc"); > + hns3_err(hw, > + "fail to zmalloc desc for handling msix error, size = %lu", > + bd_num * sizeof(struct hns3_cmd_desc)); The log is causing build error for 32bit, because of "%lu" for sizeof() output [1], fixing as "%lu" -> "%zu" while merging. Doing same for other instance below. [1] In file included from .../drivers/net/hns3/hns3_intr.c:16: .../drivers/net/hns3/hns3_intr.c: In function ‘hns3_handle_msix_error’: .../drivers/net/hns3/hns3_logs.h:16:38: error: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 6 has type ‘uint32_t’ {aka ‘unsigned int’} [-Werror=format=] 16 | rte_log(level, hns3_logtype_driver, "%s %s(): " fmt, \ | ^~~~~~~~~~~ .../drivers/net/hns3/hns3_logs.h:20:2: note: in expansion of macro ‘PMD_DRV_LOG_RAW’ 20 | PMD_DRV_LOG_RAW(hw, RTE_LOG_ERR, fmt "\n", ## args) | ^~~~~~~~~~~~~~~ .../drivers/net/hns3/hns3_intr.c:1390:3: note: in expansion of macro ‘hns3_err’ 1390 | hns3_err(hw, | ^~~~~~~~ .../drivers/net/hns3/hns3_intr.c:1391:61: note: format string is defined here 1391 | "fail to zmalloc desc for handling msix error, size = %lu", | ~~^ | | | long unsigned int | %u