From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 98A90454EF; Tue, 25 Jun 2024 13:30:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B7B642FEB; Tue, 25 Jun 2024 13:20:41 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 15D2342F77 for ; Tue, 25 Jun 2024 13:18:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314292; x=1750850292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kLR8blh+mQYmbn7jcuiBRUuoQnwRLEiivkbkbEdrS3w=; b=jBLfS8sE7trMO5XTSwCRkZc3ZDz1eWm+xkB/3W2i9YdddG9J2zFR88b2 MjssPhWVXq2eAcV1h7RyCDa3EFPygH/Okj3aJ9PSQRBvb3tMczMfOj1uC 2c2nCHQTC7QxMSiUcXN93ggGHoTUV5/GkGThNA1IB2Ic8zBORO9xNozC4 3bSpHp8+lWzXMZmIx5sDk7Mf+dkphF50rE7S1xNSYO/AwS0f52PRWmqnP wbvIu2Jfr+EEUJjFQGr2/roF0N+ZrPMbmkBmBR1G72rp2wzCi5hVMW4si UdHdo8lMTI/5tWhkA1a4iTkxN3hYk+Hx9bV+o7BwKui6OWDNzl3gZ8T95 w==; X-CSE-ConnectionGUID: 7h/5HyGqQxiZnT3tXCLeEg== X-CSE-MsgGUID: bRjaLwfUSuqSBkyqOn/ADg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080646" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080646" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:18:11 -0700 X-CSE-ConnectionGUID: 837i4FeoQLSvFKCX3KbzFQ== X-CSE-MsgGUID: ZS0KVnnBRj2BwhoSX1VxzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719771" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:11 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ben Shelton , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 119/129] net/ice/base: clean up ice_lan_tx_rx Date: Tue, 25 Jun 2024 12:14:04 +0100 Message-ID: <02293b71038228bb7435f1916497dc07eecb2305.1719313664.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ben Shelton ice_lan_tx_rx currently is missing various defines and structs. These must be in place to match sharedcode for ice devices. Add these defines which include - TIMESYNC defines - Doorbell CTX defines and struct Signed-off-by: Ben Shelton --- drivers/net/ice/base/ice_lan_tx_rx.h | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index 7be597a473..209b8e5c43 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -162,7 +162,6 @@ struct ice_fltr_desc { #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) -#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL @@ -284,6 +283,7 @@ enum ice_rx_desc_error_l3l4e_masks { enum ice_rx_l2_ptype { ICE_RX_PTYPE_L2_RESERVED = 0, ICE_RX_PTYPE_L2_MAC_PAY2 = 1, + ICE_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, ICE_RX_PTYPE_L2_FIP_PAY2 = 3, ICE_RX_PTYPE_L2_OUI_PAY2 = 4, ICE_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, @@ -343,6 +343,7 @@ enum ice_rx_ptype_inner_prot { ICE_RX_PTYPE_INNER_PROT_TCP = 2, ICE_RX_PTYPE_INNER_PROT_SCTP = 3, ICE_RX_PTYPE_INNER_PROT_ICMP = 4, + ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5, }; enum ice_rx_ptype_payload_layer { @@ -931,6 +932,8 @@ enum ice_rx_flex_desc_exstat_bits { #define ICE_RXQ_CTX_SIZE_DWORDS 8 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) +#define ICE_TXQ_CTX_SIZE_DWORDS 10 +#define ICE_TXQ_CTX_SZ (ICE_TXQ_CTX_SIZE_DWORDS * sizeof(u32)) #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800)) @@ -1071,7 +1074,7 @@ enum ice_tx_desc_len_fields { struct ice_tx_ctx_desc { __le32 tunneling_params; __le16 l2tag2; - __le16 gsc; + __le16 gcs; __le64 qw1; }; @@ -1191,6 +1194,7 @@ struct ice_tlan_ctx { u8 pkt_shaper_prof_idx; u8 gsc_ena; u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ + u16 tail; }; /* LAN Tx Completion Queue data */ @@ -1207,6 +1211,7 @@ struct ice_tx_cmpltnq { #pragma pack(1) struct ice_tx_cmpltnq_ctx { u64 base; +#define ICE_TX_CMPLTNQ_CTX_BASE_S 7 u32 q_len; #define ICE_TX_CMPLTNQ_CTX_Q_LEN_S 4 u8 generation; @@ -1214,6 +1219,9 @@ struct ice_tx_cmpltnq_ctx { u8 pf_num; u16 vmvf_num; u8 vmvf_type; +#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VF 0 +#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VMQ 1 +#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_PF 2 u8 tph_desc_wr; u8 cpuid; u32 cmpltn_cache[16]; @@ -1228,15 +1236,30 @@ struct ice_tx_drbell_fmt { u32 db; }; +/* FIXME: move to a .c file that references this variable */ +/* LAN Tx Doorbell Descriptor format info */ +static const struct ice_ctx_ele ice_tx_drbell_fmt_info[] = { + /* Field Width LSB */ + ICE_CTX_STORE(ice_tx_drbell_fmt, txq_id, 14, 0), + ICE_CTX_STORE(ice_tx_drbell_fmt, dd, 1, 14), + ICE_CTX_STORE(ice_tx_drbell_fmt, rs, 1, 15), + ICE_CTX_STORE(ice_tx_drbell_fmt, db, 32, 32), + { 0 } +}; /* LAN Tx Doorbell Queue Context */ #pragma pack(1) struct ice_tx_drbell_q_ctx { u64 base; +#define ICE_TX_DRBELL_Q_CTX_BASE_S 7 u16 ring_len; +#define ICE_TX_DRBELL_Q_CTX_RING_LEN_S 4 u8 pf_num; u16 vf_num; u8 vmvf_type; +#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VF 0 +#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VMQ 1 +#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_PF 2 u8 cpuid; u8 tph_desc_rd; u8 tph_desc_wr; @@ -1286,6 +1309,7 @@ struct ice_tx_drbell_q_ctx { /* shorter macros makes the table fit but are terse */ #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG #define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG +#define ICE_RX_PTYPE_INNER_PROT_TS ICE_RX_PTYPE_INNER_PROT_TIMESYNC /* Lookup table mapping the 10-bit HW PTYPE to the bit field for decoding */ static const struct ice_rx_ptype_decoded ice_ptype_lkup[1024] = { -- 2.43.0