From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D0DC41F45; Wed, 12 Jun 2024 17:15:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A12EC42EA0; Wed, 12 Jun 2024 17:05:27 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 0654342E72 for ; Wed, 12 Jun 2024 17:05:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204716; x=1749740716; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qGb1IVz49l84T7uXbpVRM1rmo6qoaeKI4EyzAD5wyI0=; b=IJigj3tJBqGc+vfNpxp69NrI3cP6sdQxUhT4Vv2iL2OfZGk4XXxnqtoQ snU1GEePCZ6OML25v2YFkfDTmWGVBFA/3VktbXsfSWkG1lvYfFQ/soUfq B6zK/Nea+56gvVqW638YLTjfK9q025yQknK7xe4le4jlI++lyyUE5whuK pcweDWhOGFHUY/k9qqTwM5P5XDaC/q7oQE0vl3W7Vx3+TyZHVcE2xcIlT zIq/Nmtgk0MiyCG6xH7dHVw17hIkB8sY29rMOZ8WUv1IsTNsu4WwowICW sKPixl3CJdBxycJoh+tKeUWwBPBii9UKIv7Uy9Zcqyu9edtl3uTEEz4WR A==; X-CSE-ConnectionGUID: hW7TRaV2TR6roiI9oX+Gyw== X-CSE-MsgGUID: i4wUI+itT+ie5+RM3qS64w== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459620" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459620" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:05:16 -0700 X-CSE-ConnectionGUID: aqQv6EtBS5KvoHj1pZCSnQ== X-CSE-MsgGUID: OZdXbTHISuGdGXIK1X6v5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925491" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:05:15 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: ian.stokes@intel.com, bruce.richardson@intel.com, Jacob Keller Subject: [PATCH v2 071/148] net/ice/base: match code style to upstream Date: Wed, 12 Jun 2024 16:01:05 +0100 Message-ID: <024c110f372fadf511666b6542b933cacd229895.1718204528.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The out-of-tree shared code has a few places where we differed in how the variables were used compared to the upstream. Match what's upstream to reduce the difference between the out-of-tree and upstream drivers. Signed-off-by: Jacob Keller Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 1ba8afa544..ddcadf603c 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3806,9 +3806,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port, enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) { u64 cur_freq, clk_incval, tu_per_sec, mult, adj; - u32 pmd_adj_divisor, val; - int err; u8 pmd_align; + u32 val; + int err; err = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val); if (err) { @@ -3825,9 +3825,6 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port, /* Calculate TUs per second */ tu_per_sec = cur_freq * clk_incval; - /* Get the link speed dependent PMD adjustment divisor */ - pmd_adj_divisor = e822_vernier[link_spd].pmd_adj_divisor; - /* The PMD alignment adjustment measurement depends on the link speed, * and whether FEC is enabled. For each link speed, the alignment * adjustment is calculated by dividing a value by the length of @@ -3892,7 +3889,7 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port, */ adj = DIV_U64(tu_per_sec, 125); adj *= mult; - adj = DIV_U64(adj, pmd_adj_divisor); + adj = DIV_U64(adj, e822_vernier[link_spd].pmd_adj_divisor); /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx * cycle count is necessary. @@ -3915,7 +3912,7 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port, cycle_adj = DIV_U64(tu_per_sec, 125); cycle_adj *= mult; - cycle_adj = DIV_U64(cycle_adj, pmd_adj_divisor); + cycle_adj = DIV_U64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); adj += cycle_adj; } @@ -3937,7 +3934,7 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port, cycle_adj = DIV_U64(tu_per_sec, 125); cycle_adj *= mult; - cycle_adj = DIV_U64(cycle_adj, pmd_adj_divisor); + cycle_adj = DIV_U64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); adj += cycle_adj; } -- 2.43.0