From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 50779569F for ; Fri, 23 Sep 2016 03:34:10 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP; 22 Sep 2016 18:34:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,380,1470726000"; d="scan'208";a="1034973664" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2016 18:34:09 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 22 Sep 2016 18:34:08 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 22 Sep 2016 18:34:07 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.234]) by shsmsx102.ccr.corp.intel.com ([169.254.2.15]) with mapi id 14.03.0248.002; Fri, 23 Sep 2016 09:34:04 +0800 From: "Zhang, Qi Z" To: "Yigit, Ferruh" CC: "Wu, Jingjing" , "Zhang, Helin" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 05/12] net/i40e/base: enable 25G get PHY abilities Thread-Index: AQHR/qeXkYHFtMY6WUG2Z5LO9wOxVKCFYHuAgAESIzA= Date: Fri, 23 Sep 2016 01:34:04 +0000 Message-ID: <039ED4275CED7440929022BC67E706115064D4AB@SHSMSX103.ccr.corp.intel.com> References: <1472155518-853-1-git-send-email-qi.z.zhang@intel.com> <1472155518-853-6-git-send-email-qi.z.zhang@intel.com> <950bbea5-d228-0f45-d18e-2cd9cb8f73df@intel.com> In-Reply-To: <950bbea5-d228-0f45-d18e-2cd9cb8f73df@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTZjNzBjZTItMGRiNi00NWZiLTlhMmUtYzQwNTQxOTlmNzc4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IjhUem1oTEFTYmtVdktWQ2xDRGw2bXpwN0hpT1l0Rm9sN0V6cGM3V01pTVU9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 05/12] net/i40e/base: enable 25G get PHY abilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Sep 2016 01:34:11 -0000 Hi: > -----Original Message----- > From: Yigit, Ferruh > Sent: Friday, September 23, 2016 12:54 AM > To: Zhang, Qi Z ; Wu, Jingjing ; > Zhang, Helin > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH 05/12] net/i40e/base: enable 25G get PHY > abilities >=20 > On 8/25/2016 9:05 PM, Zhang Qi wrote: > > Add extended PHY types to get PHY abilities command response struct > > for 25G, then put PHY types for 25g into the proper PHY_Type_Ext field. > > > > Signed-off-by: Zhang Qi > > --- > > drivers/net/i40e/base/i40e_adminq_cmd.h | 15 +++++++++++++-- > > drivers/net/i40e/base/i40e_common.c | 4 +++- > > 2 files changed, 16 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h > > b/drivers/net/i40e/base/i40e_adminq_cmd.h > > index 2831593..4ae4315 100644 > > --- a/drivers/net/i40e/base/i40e_adminq_cmd.h > > +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h > > @@ -1733,7 +1733,13 @@ struct i40e_aq_get_phy_abilities_resp { > > __le32 eeer_val; > > u8 d3_lpan; > > #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 > > - u8 reserved[3]; > > + u8 phy_type_ext; > > +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 > > +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 > > +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 > > +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 > > + u8 mod_type_ext; > > + u8 ext_comp_code; > > u8 phy_id[4]; > > u8 module_type[3]; > > u8 qualified_module_count; > > @@ -1755,7 +1761,12 @@ struct i40e_aq_set_phy_config { /* same bits as > above in all */ > > __le16 eee_capability; > > __le32 eeer; > > u8 low_power_ctrl; > > - u8 reserved[3]; > > + u8 phy_type_ext; > > +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 > > +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 > > +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 > > +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 >=20 > These defines looks like duplicate. >=20 >=20 This is copied from base driver, usually we will not modify the code if the= re is no critical issue. I will feedback this issue to base driver maintainer. Thanks for capture! Regards Qi