From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 97B261B902; Fri, 22 Jun 2018 15:47:25 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jun 2018 06:47:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,257,1526367600"; d="scan'208";a="49739337" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga008.fm.intel.com with ESMTP; 22 Jun 2018 06:47:24 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 22 Jun 2018 06:47:24 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 22 Jun 2018 06:47:23 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.51]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.116]) with mapi id 14.03.0319.002; Fri, 22 Jun 2018 21:47:21 +0800 From: "Zhang, Qi Z" To: "Zhao1, Wei" , "dev@dpdk.org" CC: "Lu, Wenzhuo" , "stable@dpdk.org" Thread-Topic: [PATCH] net/ixgbe: fix Tx check descriptor status APIs error Thread-Index: AQHUCgdbURLlU+aZWUajP7ZpLhIudKRsRLaw Date: Fri, 22 Jun 2018 13:47:22 +0000 Message-ID: <039ED4275CED7440929022BC67E706115323BAD2@SHSMSX103.ccr.corp.intel.com> References: <1529656727-40207-1-git-send-email-wei.zhao1@intel.com> In-Reply-To: <1529656727-40207-1-git-send-email-wei.zhao1@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiN2JlYzEyZjctZGY5Yi00YzI4LTg4NjQtOTg5NWM1OTNhOWVhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiSFNaWFozTUZ0ZWhlclBBYVREQmJBdGY1ZHVNUllIU3FkZmpxZkJNbDBNMStnb2Q4aWpCN094eUkyTWZuaDZNRiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: fix Tx check descriptor status APIs error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jun 2018 13:47:26 -0000 Hi Wei: > -----Original Message----- > From: Zhao1, Wei > Sent: Friday, June 22, 2018 4:39 PM > To: dev@dpdk.org > Cc: Lu, Wenzhuo ; Zhang, Qi Z > ; stable@dpdk.org; Zhao1, Wei > Subject: [PATCH] net/ixgbe: fix Tx check descriptor status APIs error >=20 > This is a issue involve RS bit set rule in ixgbe. > Let us take function ixgbe_xmit_pkts_vec () as an example, in this functi= on RS > bit will be set for descriptor with index > txq->tx_next_rs, and also descriptor free function > ixgbe_tx_free_bufs() also check RS bit for descriptor with index > txq->tx_next_rs, This is perfect ok. Let us take an example, > if app set tx_rs_thresh =3D 32 and nb_desc =3D 512, then ixgbe PMD code w= ill init > txq->tx_next_rs =3D 31 in function ixgbe_reset_tx_queue when tx queue set= up. > And also txq->tx_next_rs will be update as 63, 95 and so on. But, in the > function ixgbe_dev_tx_descriptor_status(), the RS bit to check is " desc = =3D ((desc > + txq->tx_rs_thresh - 1) / > txq->tx_rs_thresh) * txq-tx_rs_thresh", which is 32 ,64, 96 and so on. > So, they are all wrong! In tx function of ixgbe_xmit_pkts_simple, the RS = bit rule > is also the same, it also set index 31 ,64, 95. > we need to correct it. One question: does only the descriptor with RS bit will have DD status, or NIC will alway= s update all descriptor's DD status but this happens when the next descript= or with RS bit has been sent? If it is the first case, I think you fix still have problem, because multi-= seg mbuf or tso offload will break the 31, 63, 95 pattern See: nb_used =3D (uint16_t)(tx_pkt->nb_segs + new_ctx); if (txp !=3D NULL && nb_used + txq->nb_tx_used >=3D txq->tx_rs_t= hresh) /* set RS on the previous packet in the burst */ txp->read.cmd_type_len |=3D rte_cpu_to_le_32(IXGBE_TXD_CMD_RS); so the possible solution is store each RS position in a list at tx, and fin= d the next RS from the list in ixgbe_dev_tx_descriptor_status =20 If it is the second case, it will be simple we don't need to check forward = with tx_rs_thresh, just check the exact position ( I hope it is this case := )) Regards Qi >=20 > Fixes: a2919e13d95e ("net/ixgbe: implement descriptor status API") >=20 > Signed-off-by: Wei Zhao > --- > drivers/net/ixgbe/ixgbe_rxtx.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c > index 3e13d26..f185219 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -3146,15 +3146,15 @@ ixgbe_dev_tx_descriptor_status(void *tx_queue, > uint16_t offset) > return -EINVAL; >=20 > desc =3D txq->tx_tail + offset; > + if (desc >=3D txq->nb_tx_desc) > + desc -=3D txq->nb_tx_desc; > /* go to next desc that has the RS bit */ > - desc =3D ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * > - txq->tx_rs_thresh; > - if (desc >=3D txq->nb_tx_desc) { > + desc =3D (desc / txq->tx_rs_thresh + 1) * > + txq->tx_rs_thresh - 1; > + if (desc >=3D txq->nb_tx_desc) > desc -=3D txq->nb_tx_desc; > - if (desc >=3D txq->nb_tx_desc) > - desc -=3D txq->nb_tx_desc; > - } >=20 > + desc =3D txq->sw_ring[desc].last_id; > status =3D &txq->tx_ring[desc].wb.status; > if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)) > return RTE_ETH_TX_DESC_DONE; > -- > 2.7.5