From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 77E482F42; Thu, 15 Nov 2018 19:11:13 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Nov 2018 10:11:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,237,1539673200"; d="scan'208";a="91430616" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga006.jf.intel.com with ESMTP; 15 Nov 2018 10:11:12 -0800 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 15 Nov 2018 10:11:12 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 15 Nov 2018 10:11:11 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.161]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.214]) with mapi id 14.03.0415.000; Fri, 16 Nov 2018 02:11:09 +0800 From: "Zhang, Qi Z" To: "Xing, Beilei" , "Wu, Jingjing" CC: "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [PATCH v2] net/i40e: fix X710 Rx issue after reading some registers Thread-Index: AQHUfJGi2WoM2KILiku/GymQqls01aVRI91w Date: Thu, 15 Nov 2018 18:11:09 +0000 Message-ID: <039ED4275CED7440929022BC67E70611532E48B7@SHSMSX103.ccr.corp.intel.com> References: <1542168638-59416-1-git-send-email-beilei.xing@intel.com> <1542251822-70963-1-git-send-email-beilei.xing@intel.com> In-Reply-To: <1542251822-70963-1-git-send-email-beilei.xing@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTFjYjA0MTItMjEzNS00NTE2LTlkNmMtZDZlNDg0OWVmNGZkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidGFLYlRPS2pUN3ZqdWVzRXRwTVVBekU0bHErSVB1czhFSXBhR09zR3Z1K1dEQVgrU1MrM1wvd3Uwa1V5UUF5VzQifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/i40e: fix X710 Rx issue after reading some registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Nov 2018 18:11:14 -0000 > -----Original Message----- > From: Xing, Beilei > Sent: Wednesday, November 14, 2018 7:17 PM > To: Zhang, Qi Z ; Wu, Jingjing > Cc: dev@dpdk.org; stable@dpdk.org > Subject: [PATCH v2] net/i40e: fix X710 Rx issue after reading some regist= ers >=20 > There's an issue that X710 can't receive any packet after reading some sp= ecial > registers. That's because these registers are only valid for X722, read a= ccess for > non-X722 will cause ECC error. >=20 > Fixes: d9efd0136ac1 ("i40e: add EEPROM and registers dumping") > Cc: stable@dpdk.org >=20 > Signed-off-by: Beilei Xing Acked-by: Qi Zhang Applied to dpdk-next-net-intel. Thanks Qi > --- > v2 change: > - Add mac type as parameter in i40e_valid_regs function. >=20 > drivers/net/i40e/i40e_ethdev.c | 33 +++++++++++++++++++++++++++++++-- > 1 file changed, 31 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethde= v.c > index 1c77906..bf67a2b 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -11609,6 +11609,32 @@ i40e_dev_rx_queue_intr_disable(struct > rte_eth_dev *dev, uint16_t queue_id) > return 0; > } >=20 > +/** > + * This function is used to check if the register is valid. > + * Below is the valid registers list for X722 only: > + * 0x2b800--0x2bb00 > + * 0x38700--0x38a00 > + * 0x3d800--0x3db00 > + * 0x208e00--0x209000 > + * 0x20be00--0x20c000 > + * 0x263c00--0x264000 > + * 0x265c00--0x266000 > + */ > +static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t > +reg_offset) { > + if ((type !=3D I40E_MAC_X722) && > + ((reg_offset >=3D 0x2b800 && reg_offset <=3D 0x2bb00) || > + (reg_offset >=3D 0x38700 && reg_offset <=3D 0x38a00) || > + (reg_offset >=3D 0x3d800 && reg_offset <=3D 0x3db00) || > + (reg_offset >=3D 0x208e00 && reg_offset <=3D 0x209000) || > + (reg_offset >=3D 0x20be00 && reg_offset <=3D 0x20c000) || > + (reg_offset >=3D 0x263c00 && reg_offset <=3D 0x264000) || > + (reg_offset >=3D 0x265c00 && reg_offset <=3D 0x266000))) > + return 0; > + else > + return 1; > +} > + > static int i40e_get_regs(struct rte_eth_dev *dev, > struct rte_dev_reg_info *regs) > { > @@ -11650,8 +11676,11 @@ static int i40e_get_regs(struct rte_eth_dev > *dev, > reg_offset =3D arr_idx * reg_info->stride1 + > arr_idx2 * reg_info->stride2; > reg_offset +=3D reg_info->base_addr; > - ptr_data[reg_offset >> 2] =3D > - I40E_READ_REG(hw, reg_offset); > + if (!i40e_valid_regs(hw->mac.type, reg_offset)) > + ptr_data[reg_offset >> 2] =3D 0; > + else > + ptr_data[reg_offset >> 2] =3D > + I40E_READ_REG(hw, reg_offset); > } > } >=20 > -- > 2.5.5