From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 0564B2B9E for ; Tue, 20 Nov 2018 05:17:00 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Nov 2018 20:16:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,255,1539673200"; d="scan'208";a="109704100" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga001.jf.intel.com with ESMTP; 19 Nov 2018 20:16:59 -0800 Received: from fmsmsx161.amr.corp.intel.com (10.18.125.9) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 19 Nov 2018 20:16:59 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX161.amr.corp.intel.com (10.18.125.9) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 19 Nov 2018 20:16:58 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.161]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.214]) with mapi id 14.03.0415.000; Tue, 20 Nov 2018 12:16:56 +0800 From: "Zhang, Qi Z" To: "Zhao1, Wei" , "Player, Timmons" CC: "dev@dpdk.org" , "Lu, Wenzhuo" Thread-Topic: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using MSI-X Thread-Index: AQHUgIFHKT2C+qw/uEOM/wfsS9EivqVYDqXA Date: Tue, 20 Nov 2018 04:16:56 +0000 Message-ID: <039ED4275CED7440929022BC67E70611532E87A4@SHSMSX103.ccr.corp.intel.com> References: <20181119144833.7732-1-timmons.player@spirent.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTEyODFmNGMtNjFjYS00YWNmLTk3MGQtMGQ4ZmUzMWFmOTMxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiVkRNMjFpbTB0a2dJNCtlVGJsZVhzcFJuM3VhMmhDVXhzY0ZiZzNlRGh6dHdIcWpXeUczODJtTWpYNVJ5UEtFbyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using MSI-X X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Nov 2018 04:17:02 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Zhao1, Wei > Sent: Monday, November 19, 2018 7:29 PM > To: Player, Timmons > Cc: dev@dpdk.org; Lu, Wenzhuo > Subject: Re: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using = MSI-X >=20 > Acked-by: Wei Zhao Applied to dpdk-next-net-intel. Thanks Qi >=20 > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Player, Timmons > > Sent: Monday, November 19, 2018 10:49 PM > > To: Lu, Wenzhuo > > Cc: dev@dpdk.org; Player, Timmons > > Subject: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using > > MSI-X > > > > Take the 'other interrupt' into account when setting up MSI-X > > interrupts and use the proper mask when enabling it. > > Also, rearm the MSI-X vector after the LSC interrupt fires. > > > > This change allows both LSC and RXQ interrupts to work at the same > > time when using MSI-X interrupts. > > > > Signed-off-by: Timmons C. Player > > --- > > v2: > > * Update igb_intr_{enable,disable} to only touch the 'other interrupt' > > when it is explicitly enabled. > > > > drivers/net/e1000/igb_ethdev.c | 43 +++++++++++++++++++++++++++++- > > ---- > > 1 file changed, 37 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/net/e1000/igb_ethdev.c > > b/drivers/net/e1000/igb_ethdev.c index d9d29d22f..87c9aedf2 100644 > > --- a/drivers/net/e1000/igb_ethdev.c > > +++ b/drivers/net/e1000/igb_ethdev.c > > @@ -68,6 +68,9 @@ > > #define E1000_VET_VET_EXT 0xFFFF0000 > > #define E1000_VET_VET_EXT_SHIFT 16 > > > > +/* MSI-X other interrupt vector */ > > +#define IGB_MSIX_OTHER_INTR_VEC 0 > > + > > static int eth_igb_configure(struct rte_eth_dev *dev); static int > > eth_igb_start(struct rte_eth_dev *dev); static void > > eth_igb_stop(struct rte_eth_dev *dev); @@ -138,7 +141,7 @@ static void > > igb_vlan_hw_extend_disable(struct rte_eth_dev *dev); static int > > eth_igb_led_on(struct rte_eth_dev *dev); static int > > eth_igb_led_off(struct rte_eth_dev *dev); > > > > -static void igb_intr_disable(struct e1000_hw *hw); > > +static void igb_intr_disable(struct rte_eth_dev *dev); > > static int igb_get_rx_buffer_size(struct e1000_hw *hw); static int > > eth_igb_rar_set(struct rte_eth_dev *dev, > > struct ether_addr *mac_addr, > > @@ -538,14 +541,31 @@ igb_intr_enable(struct rte_eth_dev *dev) > > E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); > > struct e1000_hw *hw =3D > > E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > > + > > + if (rte_intr_allow_others(intr_handle) && > > + dev->data->dev_conf.intr_conf.lsc !=3D 0) { > > + E1000_WRITE_REG(hw, E1000_EIMS, 1 << > > IGB_MSIX_OTHER_INTR_VEC); > > + } > > > > E1000_WRITE_REG(hw, E1000_IMS, intr->mask); > > E1000_WRITE_FLUSH(hw); > > } > > > > static void > > -igb_intr_disable(struct e1000_hw *hw) > > +igb_intr_disable(struct rte_eth_dev *dev) > > { > > + struct e1000_hw *hw =3D > > + E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > > + > > + if (rte_intr_allow_others(intr_handle) && > > + dev->data->dev_conf.intr_conf.lsc !=3D 0) { > > + E1000_WRITE_REG(hw, E1000_EIMC, 1 << > > IGB_MSIX_OTHER_INTR_VEC); > > + } > > + > > E1000_WRITE_REG(hw, E1000_IMC, ~0); > > E1000_WRITE_FLUSH(hw); > > } > > @@ -1486,7 +1506,7 @@ eth_igb_stop(struct rte_eth_dev *dev) > > > > eth_igb_rxtx_control(dev, false); > > > > - igb_intr_disable(hw); > > + igb_intr_disable(dev); > > > > /* disable intr eventfd mapping */ > > rte_intr_disable(intr_handle); > > @@ -2768,12 +2788,15 @@ static int eth_igb_rxq_interrupt_setup(struct > > rte_eth_dev *dev) > > uint32_t mask, regval; > > struct e1000_hw *hw =3D > > E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > > + int misc_shift =3D rte_intr_allow_others(intr_handle) ? 1 : 0; > > struct rte_eth_dev_info dev_info; > > > > memset(&dev_info, 0, sizeof(dev_info)); > > eth_igb_infos_get(dev, &dev_info); > > > > - mask =3D 0xFFFFFFFF >> (32 - dev_info.max_rx_queues); > > + mask =3D (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << > > misc_shift; > > regval =3D E1000_READ_REG(hw, E1000_EIMS); > > E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); > > > > @@ -2800,7 +2823,7 @@ eth_igb_interrupt_get_status(struct rte_eth_dev > > *dev) > > struct e1000_interrupt *intr =3D > > E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); > > > > - igb_intr_disable(hw); > > + igb_intr_disable(dev); > > > > /* read-on-clear nic registers here */ > > icr =3D E1000_READ_REG(hw, E1000_ICR); @@ -5583,13 +5606,17 @@ > > eth_igb_configure_msix_intr(struct rte_eth_dev > > *dev) > > E1000_GPIE_NSICR); > > intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << > > misc_shift; > > + > > + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) > > + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); > > + > > regval =3D E1000_READ_REG(hw, E1000_EIAC); > > E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); > > > > /* enable msix_other interrupt */ > > regval =3D E1000_READ_REG(hw, E1000_EIMS); > > E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); > > - tmpval =3D (dev->data->nb_rx_queues | E1000_IVAR_VALID) > > << 8; > > + tmpval =3D (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) > > << 8; > > E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); > > } > > > > @@ -5598,6 +5625,10 @@ eth_igb_configure_msix_intr(struct rte_eth_dev > > *dev) > > */ > > intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << > > misc_shift; > > + > > + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) > > + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); > > + > > regval =3D E1000_READ_REG(hw, E1000_EIAM); > > E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); > > > > -- > > 2.17.1