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Thu, 29 Aug 2019 16:31:53 -0700 Received: from fmsmsx607.amr.corp.intel.com (10.18.126.87) by fmsmsx607.amr.corp.intel.com (10.18.126.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 29 Aug 2019 16:31:52 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx607.amr.corp.intel.com (10.18.126.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 29 Aug 2019 16:31:52 -0700 Received: from shsmsx105.ccr.corp.intel.com ([169.254.11.15]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.112]) with mapi id 14.03.0439.000; Fri, 30 Aug 2019 07:31:51 +0800 From: "Zhang, Qi Z" To: "Rong, Leyi" , "Ye, Xiaolong" , "Wang, Haiyue" , "Lu, Wenzhuo" CC: "dev@dpdk.org" Thread-Topic: [PATCH v2 6/6] net/ice: switch to Rx flexible descriptor in AVX path Thread-Index: AQHVXkCqWI6HcDOJHE66dgkVWVdbbKcSxSYQ Date: Thu, 29 Aug 2019 23:31:50 +0000 Message-ID: <039ED4275CED7440929022BC67E7061153D8671C@SHSMSX105.ccr.corp.intel.com> References: <20190829023421.112551-2-leyi.rong@intel.com> <20190829080441.12602-1-leyi.rong@intel.com> <20190829080441.12602-7-leyi.rong@intel.com> In-Reply-To: <20190829080441.12602-7-leyi.rong@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTY5MmM3NDYtNTBhOC00NGIwLTk0MWMtOTUxNTgyZDdlY2NhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiYklVQkJra0VXQTZRZVpmRHlVXC93TTZLdnoxMU9SWmVsNDRINTBLTXp6TUlYclVCODB0ZCtoR3Ywd3lFWmtLZlYifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 6/6] net/ice: switch to Rx flexible descriptor in AVX path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Rong, Leyi > Sent: Thursday, August 29, 2019 4:05 PM > To: Zhang, Qi Z ; Ye, Xiaolong > ; Wang, Haiyue ; Lu, > Wenzhuo > Cc: dev@dpdk.org; Rong, Leyi > Subject: [PATCH v2 6/6] net/ice: switch to Rx flexible descriptor in AVX = path >=20 > Switch to Rx flexible descriptor format instead of legacy descriptor form= at. >=20 > Signed-off-by: Leyi Rong > --- > drivers/net/ice/ice_rxtx_vec_avx2.c | 232 ++++++++++++++-------------- > 1 file changed, 118 insertions(+), 114 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c > b/drivers/net/ice/ice_rxtx_vec_avx2.c > index 5ce29c2a2..158f17d80 100644 > --- a/drivers/net/ice/ice_rxtx_vec_avx2.c > +++ b/drivers/net/ice/ice_rxtx_vec_avx2.c > @@ -15,10 +15,10 @@ ice_rxq_rearm(struct ice_rx_queue *rxq) { > int i; > uint16_t rx_id; > - volatile union ice_rx_desc *rxdp; > + volatile union ice_rx_flex_desc *rxdp; > struct ice_rx_entry *rxep =3D &rxq->sw_ring[rxq->rxrearm_start]; >=20 > - rxdp =3D rxq->rx_ring + rxq->rxrearm_start; > + rxdp =3D (union ice_rx_flex_desc *)rxq->rx_ring + rxq->rxrearm_start; Since after this patch, all data paths (normal, sse, avx2) are moved to fle= x desc,=20 Ice_rx_desc is not used anymore, so can replace all of them with ice_rx_fle= x_desc,=20 then above convention can be avoid. <.......> > * take the two sets of status bits and merge to one @@ -450,20 > +452,22 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct > rte_mbuf **rx_pkts, > /* get only flag/error bits we want */ > const __m256i flag_bits =3D > _mm256_and_si256(status0_7, flags_mask); > - /* set vlan and rss flags */ > - const __m256i vlan_flags =3D > - _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits); > - const __m256i rss_flags =3D > - _mm256_shuffle_epi8(rss_flags_shuf, > - _mm256_srli_epi32(flag_bits, 11)); > /** > * l3_l4_error flags, shuffle, then shift to correct adjustment > * of flags in flags_shuf, and finally mask out extra bits > */ > __m256i l3_l4_flags =3D _mm256_shuffle_epi8(l3_l4_flags_shuf, > - _mm256_srli_epi32(flag_bits, 22)); > + _mm256_srli_epi32(flag_bits, 4)); > l3_l4_flags =3D _mm256_slli_epi32(l3_l4_flags, 1); > l3_l4_flags =3D _mm256_and_si256(l3_l4_flags, cksum_mask); > + /* set rss and vlan flags */ > + const __m256i rss_vlan_flag_bits =3D > + _mm256_srli_epi32(flag_bits, 12); > + const __m256i rss_flags =3D > + _mm256_shuffle_epi8(rss_flags_shuf, rss_vlan_flag_bits); > + const __m256i vlan_flags =3D > + _mm256_shuffle_epi8(vlan_flags_shuf, > + rss_vlan_flag_bits); Seems we can "or" rss_flags_shuf and vlan_flags_shuf, so just need to do on= e shuffle here to save some CPU cycles? >=20 > /* merge flags */ > const __m256i mbuf_flags =3D _mm256_or_si256(l3_l4_flags, > -- > 2.17.1