From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA19DA0613 for ; Sat, 28 Sep 2019 03:03:47 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2499B1BE84; Sat, 28 Sep 2019 03:03:46 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id D33DE1BE82 for ; Sat, 28 Sep 2019 03:03:43 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Sep 2019 18:03:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,557,1559545200"; d="scan'208";a="190506634" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga007.fm.intel.com with ESMTP; 27 Sep 2019 18:03:42 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 27 Sep 2019 18:03:42 -0700 Received: from shsmsx153.ccr.corp.intel.com (10.239.6.53) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 27 Sep 2019 18:03:42 -0700 Received: from shsmsx105.ccr.corp.intel.com ([169.254.11.23]) by SHSMSX153.ccr.corp.intel.com ([169.254.12.235]) with mapi id 14.03.0439.000; Sat, 28 Sep 2019 09:03:40 +0800 From: "Zhang, Qi Z" To: "Su, Simei" , "Wu, Jingjing" , "Ye, Xiaolong" CC: "dev@dpdk.org" Thread-Topic: [PATCH v4 2/3] ethdev: extend RSS offload types Thread-Index: AQHVdREsS1FD3DnUXU+6b8/c+ZAUMKdAReUw Date: Sat, 28 Sep 2019 01:03:40 +0000 Message-ID: <039ED4275CED7440929022BC67E7061153D9F306@SHSMSX105.ccr.corp.intel.com> References: <1569420404-163301-1-git-send-email-simei.su@intel.com> <1569574449-47991-1-git-send-email-simei.su@intel.com> <1569574449-47991-3-git-send-email-simei.su@intel.com> In-Reply-To: <1569574449-47991-3-git-send-email-simei.su@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTBlMDUyN2EtZjgwMi00NzY3LTgzZWQtOTQwNjUyYjlhOGIwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoicXhlVmE1YXVcL0p5cFIxcTRTSkJmQkkxUGQ3NWdqQStkb0xVamJuSkZNUXhid0t1RnFWRHAxYXBNZ3RxK3dqWHMifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 2/3] ethdev: extend RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Su, Simei > Sent: Friday, September 27, 2019 4:54 PM > To: Zhang, Qi Z ; Wu, Jingjing ; > Ye, Xiaolong > Cc: dev@dpdk.org; Su, Simei > Subject: [PATCH v4 2/3] ethdev: extend RSS offload types >=20 > This patch reserves several bits as input set selection from the high end= of the > 64 bits. It is combined with exisiting ETH_RSS_* to represent rss types. >=20 > for example: > ETH_RSS_IPV4 | ETH_RSS_L3_SRC_ONLY: hash on src ip address only > ETH_RSS_IPV4_UDP | ETH_RSS_L4_DST_ONLY: hash on src/dst IP and > dst UDP port >=20 > Signed-off-by: Simei Su > --- > lib/librte_ethdev/rte_ethdev.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) >=20 > diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethde= v.h > index 1605467..106b67f 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -505,6 +505,19 @@ struct rte_eth_rss_conf { > #define ETH_RSS_GENEVE (1ULL << 20) > #define ETH_RSS_NVGRE (1ULL << 21) >=20 > +/* > + * We use the following macros to combine with above ETH_RSS_* for > + * more specific input set selection. These bits are defined starting > + * from the high end of the 64 bits. > + * Note: If we use above ETH_RSS_* without SRC/DST_ONLY, it represents > + * both SRC and DST are taken into account. SRC_ONLY and DST_ONLY can't To be more accurate, should be SRC_ONLY and DST_ONLY of the same level can'= t be used simultaneously. > + * be used simultaneously. > + */ > +#define ETH_RSS_L3_SRC_ONLY (1ULL << 63) > +#define ETH_RSS_L3_DST_ONLY (1ULL << 62) > +#define ETH_RSS_L4_SRC_ONLY (1ULL << 61) > +#define ETH_RSS_L4_DST_ONLY (1ULL << 60) > + > #define ETH_RSS_IP ( \ > ETH_RSS_IPV4 | \ > ETH_RSS_FRAG_IPV4 | \ > -- > 1.8.3.1