From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97FEAA04AB; Tue, 12 Nov 2019 02:56:07 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6A41223D; Tue, 12 Nov 2019 02:56:07 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 4AA4D237 for ; Tue, 12 Nov 2019 02:56:05 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Nov 2019 17:56:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,294,1569308400"; d="scan'208";a="207299713" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga006.jf.intel.com with ESMTP; 11 Nov 2019 17:56:03 -0800 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 11 Nov 2019 17:56:02 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 11 Nov 2019 17:56:02 -0800 Received: from shsmsx105.ccr.corp.intel.com ([169.254.11.225]) by shsmsx102.ccr.corp.intel.com ([169.254.2.108]) with mapi id 14.03.0439.000; Tue, 12 Nov 2019 09:56:00 +0800 From: "Zhang, Qi Z" To: "Rong, Leyi" , "Lu, Wenzhuo" , "Ye, Xiaolong" CC: "dev@dpdk.org" Thread-Topic: [PATCH] net/iavf: set CMD bit2 to 1 in Tx Desc of AVX Tx path Thread-Index: AQHVlSvmEGEaAVIRnkyWS2iJNL2nMaeGx7aA Date: Tue, 12 Nov 2019 01:55:59 +0000 Message-ID: <039ED4275CED7440929022BC67E7061153DC7CBA@SHSMSX105.ccr.corp.intel.com> References: <20191107052144.78380-1-leyi.rong@intel.com> In-Reply-To: <20191107052144.78380-1-leyi.rong@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOGE4OTE5MGEtNGNiMi00NDI4LWI3NTEtMjU5MDZmM2MyNzMyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiaFwvdGlUbE5VSktKTnVLN0RMSGtueHNsWUdSTm5ldkIwMitcL2NldjUxb0dtajhpa2p3dU9zTlA3QkNMVWNLa1wvdiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/iavf: set CMD bit2 to 1 in Tx Desc of AVX Tx path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Rong, Leyi > Sent: Thursday, November 7, 2019 1:22 PM > To: Lu, Wenzhuo ; Zhang, Qi Z > ; Ye, Xiaolong > Cc: dev@dpdk.org; Rong, Leyi > Subject: [PATCH] net/iavf: set CMD bit2 to 1 in Tx Desc of AVX Tx path >=20 > Fix iavf vf_checksum_sw case fail in X710/XXV710, set bit2 to 1 of CMD fi= eld in > Tx descriptor of AVX Tx path according to Spec. >=20 > Fixes: af0c246a3800 ("net/iavf: enable AVX2 for iavf") >=20 > Signed-off-by: Leyi Rong > --- > drivers/net/iavf/iavf_rxtx_vec_avx2.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c > b/drivers/net/iavf/iavf_rxtx_vec_avx2.c > index f0c00be56..2c7375576 100644 > --- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c > +++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c > @@ -785,8 +785,9 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, > struct rte_mbuf **tx_pkts, > volatile struct iavf_tx_desc *txdp; > struct iavf_tx_entry *txep; > uint16_t n, nb_commit, tx_id; > - uint64_t flags =3D IAVF_TX_DESC_CMD_EOP; > - uint64_t rs =3D IAVF_TX_DESC_CMD_RS | IAVF_TX_DESC_CMD_EOP; > + /* bit2 is reserved and must be set to 1 according to Spec */ > + uint64_t flags =3D IAVF_TX_DESC_CMD_EOP | 0x04; Better to use macro IAVF_TX_DESC_CMD_ICRC to replace 0x4 > + uint64_t rs =3D IAVF_TX_DESC_CMD_RS | flags; >=20 > /* cross rx_thresh boundary is not allowed */ > nb_pkts =3D RTE_MIN(nb_pkts, txq->rs_thresh); > -- > 2.17.1