From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83F13A0540; Mon, 20 Jul 2020 11:50:59 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 14C4E29CB; Mon, 20 Jul 2020 11:50:58 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 79AF71AFB; Mon, 20 Jul 2020 11:50:56 +0200 (CEST) IronPort-SDR: k9ob4PIZLL/0VyVHMWotT+y+ULluaqh/mIc1gl1etYqNwuuS6c7vLAxEVwJpw98XLtXepsLlh1 ZLDWJtHm63AA== X-IronPort-AV: E=McAfee;i="6000,8403,9687"; a="129960581" X-IronPort-AV: E=Sophos;i="5.75,374,1589266800"; d="scan'208";a="129960581" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2020 02:50:54 -0700 IronPort-SDR: JKHxEXyGytEIsTPe/ZSH9mK26Zdw0LWpPzbrTtj+jjVcqu2XRjgcFyqR5GrnBFA493lYX4VnhB E4MnhW2rmxYw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,374,1589266800"; d="scan'208";a="461627879" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga005.jf.intel.com with ESMTP; 20 Jul 2020 02:50:54 -0700 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 20 Jul 2020 02:50:53 -0700 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 20 Jul 2020 02:50:53 -0700 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Mon, 20 Jul 2020 02:50:53 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.22]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.32]) with mapi id 14.03.0439.000; Mon, 20 Jul 2020 17:50:50 +0800 From: "Zhang, Qi Z" To: "Jiang, JunyuX" , "dev@dpdk.org" CC: "Yang, Qiming" , "stable@dpdk.org" Thread-Topic: [PATCH v2] net/ice: fix incorrect Rx/Tx bytes statistics Thread-Index: AQHWW+L90WaLM0v8UUustJ59PP9tsakQPaTw Date: Mon, 20 Jul 2020 09:50:49 +0000 Message-ID: <039ED4275CED7440929022BC67E7061154862515@SHSMSX103.ccr.corp.intel.com> References: <20200715070307.36814-1-junyux.jiang@intel.com> <20200717021747.52132-1-junyux.jiang@intel.com> In-Reply-To: <20200717021747.52132-1-junyux.jiang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/ice: fix incorrect Rx/Tx bytes statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Jiang, JunyuX > Sent: Friday, July 17, 2020 10:18 AM > To: dev@dpdk.org > Cc: Zhang, Qi Z ; Yang, Qiming > ; Jiang, JunyuX ; > stable@dpdk.org > Subject: [PATCH v2] net/ice: fix incorrect Rx/Tx bytes statistics >=20 > This patch fixed the issue that rx/tx bytes overflowed on 40 bit limitati= on by > enlarging the limitation. >=20 > Fixes: a37bde56314d ("net/ice: support statistics") > Cc: stable@dpdk.org >=20 > Signed-off-by: Junyu Jiang > --- > drivers/net/ice/ice_ethdev.c | 36 ++++++++++++++++++++++++++++++++++++ > drivers/net/ice/ice_ethdev.h | 4 ++++ > 2 files changed, 40 insertions(+) >=20 > diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c = index > 3534d18ca..85aa6cfe6 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -4139,6 +4139,10 @@ ice_stat_update_40(struct ice_hw *hw, static > void ice_update_vsi_stats(struct ice_vsi *vsi) { > + uint64_t old_rx_bytes_h =3D vsi->old_rx_bytes & ~ICE_40_BIT_MASK; > + uint64_t old_rx_bytes_l =3D vsi->old_rx_bytes & ICE_40_BIT_MASK; > + uint64_t old_tx_bytes_h =3D vsi->old_tx_bytes & ~ICE_40_BIT_MASK; > + uint64_t old_tx_bytes_l =3D vsi->old_tx_bytes & ICE_40_BIT_MASK; Could you use a macro to replace above variable? so above variable is not n= ecessary #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK); =20 #define ICE_RXTX_BYTES_HIGH .... > struct ice_eth_stats *oes =3D &vsi->eth_stats_offset; > struct ice_eth_stats *nes =3D &vsi->eth_stats; > struct ice_hw *hw =3D ICE_VSI_TO_HW(vsi); @@ -4156,6 +4160,13 @@ > ice_update_vsi_stats(struct ice_vsi *vsi) > ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), > vsi->offset_loaded, &oes->rx_broadcast, > &nes->rx_broadcast); > + /* enlarge the limitation when rx_bytes overflowed */ > + if (vsi->offset_loaded) { > + if (old_rx_bytes_l > nes->rx_bytes) > + old_rx_bytes_h +=3D (uint64_t)1 << ICE_40_BIT_WIDTH; > + nes->rx_bytes +=3D old_rx_bytes_h; > + } > + vsi->old_rx_bytes =3D nes->rx_bytes; > /* exclude CRC bytes */ > nes->rx_bytes -=3D (nes->rx_unicast + nes->rx_multicast + > nes->rx_broadcast) * RTE_ETHER_CRC_LEN; @@ -4182,6 > +4193,13 @@ ice_update_vsi_stats(struct ice_vsi *vsi) > /* GLV_TDPC not supported */ > ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, > &oes->tx_errors, &nes->tx_errors); > + /* enlarge the limitation when tx_bytes overflowed */ > + if (vsi->offset_loaded) { > + if (old_tx_bytes_l > nes->tx_bytes) > + old_tx_bytes_h +=3D (uint64_t)1 << ICE_40_BIT_WIDTH; > + nes->tx_bytes +=3D old_tx_bytes_h; > + } > + vsi->old_tx_bytes =3D nes->tx_bytes; > vsi->offset_loaded =3D true; >=20 > PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start > **************", @@ -4206,6 +4224,10 @@ ice_update_vsi_stats(struct > ice_vsi *vsi) static void ice_read_stats_registers(struct ice_pf *pf, s= truct > ice_hw *hw) { > + uint64_t old_rx_bytes_h =3D pf->old_rx_bytes & ~ICE_40_BIT_MASK; > + uint64_t old_rx_bytes_l =3D pf->old_rx_bytes & ICE_40_BIT_MASK; > + uint64_t old_tx_bytes_h =3D pf->old_tx_bytes & ~ICE_40_BIT_MASK; > + uint64_t old_tx_bytes_l =3D pf->old_tx_bytes & ICE_40_BIT_MASK; > struct ice_hw_port_stats *ns =3D &pf->stats; /* new stats */ > struct ice_hw_port_stats *os =3D &pf->stats_offset; /* old stats */ >=20 > @@ -4229,6 +4251,13 @@ ice_read_stats_registers(struct ice_pf *pf, struct > ice_hw *hw) > ice_stat_update_32(hw, PRTRPB_RDPC, > pf->offset_loaded, &os->eth.rx_discards, > &ns->eth.rx_discards); > + /* enlarge the limitation when rx_bytes overflowed */ > + if (pf->offset_loaded) { > + if (old_rx_bytes_l > ns->eth.rx_bytes) > + old_rx_bytes_h +=3D (uint64_t)1 << ICE_40_BIT_WIDTH; > + ns->eth.rx_bytes +=3D old_rx_bytes_h; > + } > + pf->old_rx_bytes =3D ns->eth.rx_bytes; >=20 > /* Workaround: CRC size should not be included in byte statistics, > * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx > @@ -4259,6 +4288,13 @@ ice_read_stats_registers(struct ice_pf *pf, struct > ice_hw *hw) > GLPRT_BPTCL(hw->port_info->lport), > pf->offset_loaded, &os->eth.tx_broadcast, > &ns->eth.tx_broadcast); > + /* enlarge the limitation when tx_bytes overflowed */ > + if (pf->offset_loaded) { > + if (old_tx_bytes_l > ns->eth.tx_bytes) > + old_tx_bytes_h +=3D (uint64_t)1 << ICE_40_BIT_WIDTH; > + ns->eth.tx_bytes +=3D old_tx_bytes_h; > + } > + pf->old_tx_bytes =3D ns->eth.tx_bytes; > ns->eth.tx_bytes -=3D (ns->eth.tx_unicast + ns->eth.tx_multicast + > ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; >=20 > diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h = index > 2bff735ca..69fd35b47 100644 > --- a/drivers/net/ice/ice_ethdev.h > +++ b/drivers/net/ice/ice_ethdev.h > @@ -248,6 +248,8 @@ struct ice_vsi { > struct ice_eth_stats eth_stats_offset; > struct ice_eth_stats eth_stats; > bool offset_loaded; > + uint64_t old_rx_bytes; > + uint64_t old_tx_bytes; > }; >=20 > enum proto_xtr_type { > @@ -391,6 +393,8 @@ struct ice_pf { > struct ice_parser_list perm_parser_list; > struct ice_parser_list dist_parser_list; > bool init_link_up; > + uint64_t old_rx_bytes; > + uint64_t old_tx_bytes; > }; >=20 > #define ICE_MAX_QUEUE_NUM 2048 > -- > 2.17.1