From: Yongseok Koh <yskoh@mellanox.com>
To: "herbert.guan@arm.com" <herbert.guan@arm.com>,
Gavin Hu <gavin.hu@arm.com>,
"jerinj@marvell.com" <jerinj@marvell.com>,
Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
Cc: dev <dev@dpdk.org>, Russell Peterson <russell@mellanox.com>,
Mark Rosenbluth <mrosenbluth@mellanox.com>
Subject: [dpdk-dev] Default cacheline size for ARM
Date: Fri, 4 Jan 2019 19:59:13 +0000 [thread overview]
Message-ID: <045CAEC7-8CEE-40AE-B63A-E4A7CE312594@mellanox.com> (raw)
Hi,
The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be 128B by
default. Mellanox's BlueField is an ARM CPU having Cortex-A72 and its CL size is
64B.
I can add config/defconfig_arm64-bluefield-linuxapp-gcc for legacy build anyway.
For the meson build, I know it parses the Main ID register to figure out
Implementor ID and Part Number. However, Mellanox doesn't program our own ID yet
but we set the Part Number as 0xd08 (A72).
According to my folks, ARM's A53, A57, A72, and A73 designs all have 64B CL. If
that's true, can I push a patch to make the change?
Please comment.
Thanks,
Yongseok
next reply other threads:[~2019-01-04 19:59 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-04 19:59 Yongseok Koh [this message]
2019-01-05 5:14 ` [dpdk-dev] [EXT] " Jerin Jacob Kollanukkaran
2019-01-05 22:47 ` Honnappa Nagarahalli
2019-01-06 7:56 ` Jerin Jacob Kollanukkaran
2019-01-14 7:47 ` Honnappa Nagarahalli
2019-01-14 8:05 ` Jerin Jacob Kollanukkaran
2019-01-16 1:57 ` Honnappa Nagarahalli
2019-01-18 5:50 ` Honnappa Nagarahalli
2019-01-23 9:05 ` Jerin Jacob Kollanukkaran
2019-01-23 16:28 ` Honnappa Nagarahalli
2019-01-28 12:56 ` Jerin Jacob Kollanukkaran
2019-01-31 18:09 ` Honnappa Nagarahalli
2019-02-01 17:16 ` Jerin Jacob Kollanukkaran
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