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Fri, 4 Jan 2019 19:59:13 +0000 From: Yongseok Koh To: "herbert.guan@arm.com" , Gavin Hu , "jerinj@marvell.com" , Honnappa Nagarahalli CC: dev , Russell Peterson , Mark Rosenbluth Thread-Topic: Default cacheline size for ARM Thread-Index: AQHUpGf3rBLpFT4jLEKyP25u6LLEjA== Date: Fri, 4 Jan 2019 19:59:13 +0000 Message-ID: <045CAEC7-8CEE-40AE-B63A-E4A7CE312594@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB3PR0502MB4028; 6:hlF7SLqre5zf3h3YDjiRFzZTv8feqRN/xflwAYI6zIZZmM6Hb5PApkq/ls/REaKdJYaxp2C1Gm8YrcEB7jsWzI5lbocNVafuHs78kO/ExZPPDOr1vIV7x6CWechHaFzL98k+IleSK5mCSeA1B8OQq3spQeBCjaPDzXSHHqYgIO3GkkeWY5aM4CSd/ZzsVTLZi5OtH0n2Un9kqRXPajyF4ByIsDyCc4NHURG+uo4QzrmKQyKZhOZvhqLmNk5NAiDIOslzbMaMb8i3MfTZl6i++ufqqwN5wJyMFzm1cifh6X8Cms3adXEGnr4cA6xCjq1l2vecqpv5X5LDGrTx4fJNhVHsXDZG3UZOUvfGINuqVsIgWA3HUIxwBb++QNnygHEp8KOg0PgV85Dwm09NIO6AR1q4raYM4wlYJBHVswtsnBajDkHBGbRQZPOR1yHEcuXlNc15uV34DE+CDxRlri5jjA==; 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charset="us-ascii" Content-ID: <5F70A39EA5F54F4781D762499DF3E788@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2345ca16-2dd2-4591-dc00-08d6727f19d6 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Jan 2019 19:59:13.8077 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4028 Subject: [dpdk-dev] Default cacheline size for ARM X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Jan 2019 19:59:15 -0000 Hi, The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be 128B by default. Mellanox's BlueField is an ARM CPU having Cortex-A72 and its CL si= ze is 64B. I can add config/defconfig_arm64-bluefield-linuxapp-gcc for legacy build an= yway. For the meson build, I know it parses the Main ID register to figure out Implementor ID and Part Number. However, Mellanox doesn't program our own I= D yet but we set the Part Number as 0xd08 (A72). According to my folks, ARM's A53, A57, A72, and A73 designs all have 64B CL= . If that's true, can I push a patch to make the change? Please comment. Thanks, Yongseok