From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3403A04C8; Fri, 18 Sep 2020 15:44:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CDB7A1D993; Fri, 18 Sep 2020 15:44:58 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by dpdk.org (Postfix) with ESMTP id 55DF51D95C for ; Fri, 18 Sep 2020 15:44:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1600436696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:autocrypt:autocrypt; bh=opOAGw6G/Q5BnEV6/IORuWQUYe26dnbOPFED//Iy0vw=; b=WEORcDhQ4TnbW5SaytV9TOoGh+0HA75fya+xQPCxwWsUM5wonClLvejMs7OdkiCKwZDlLc j3PeHvO4easUpYonqXHRqNY58OTnTr7SGlqb0mmtrsQsfHBLSoD/mfEiIOdL1I8jrIbGTD dBOXwEkriAG4/JF8LHKJg1OZ2V0XPMg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-40-83lOuQjpPx2SPsFfE3ln4w-1; Fri, 18 Sep 2020 09:44:55 -0400 X-MC-Unique: 83lOuQjpPx2SPsFfE3ln4w-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E7953802EA5; Fri, 18 Sep 2020 13:44:53 +0000 (UTC) Received: from [10.36.110.9] (unknown [10.36.110.9]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 76A1F60BEC; Fri, 18 Sep 2020 13:44:52 +0000 (UTC) To: Marvin Liu , chenbo.xia@intel.com, zhihong.wang@intel.com Cc: dev@dpdk.org References: <20200819032414.51430-1-yong.liu@intel.com> <20200819032414.51430-5-yong.liu@intel.com> From: Maxime Coquelin Autocrypt: addr=maxime.coquelin@redhat.com; keydata= mQINBFOEQQIBEADjNLYZZqghYuWv1nlLisptPJp+TSxE/KuP7x47e1Gr5/oMDJ1OKNG8rlNg kLgBQUki3voWhUbMb69ybqdMUHOl21DGCj0BTU3lXwapYXOAnsh8q6RRM+deUpasyT+Jvf3a gU35dgZcomRh5HPmKMU4KfeA38cVUebsFec1HuJAWzOb/UdtQkYyZR4rbzw8SbsOemtMtwOx YdXodneQD7KuRU9IhJKiEfipwqk2pufm2VSGl570l5ANyWMA/XADNhcEXhpkZ1Iwj3TWO7XR uH4xfvPl8nBsLo/EbEI7fbuUULcAnHfowQslPUm6/yaGv6cT5160SPXT1t8U9QDO6aTSo59N jH519JS8oeKZB1n1eLDslCfBpIpWkW8ZElGkOGWAN0vmpLfdyiqBNNyS3eGAfMkJ6b1A24un /TKc6j2QxM0QK4yZGfAxDxtvDv9LFXec8ENJYsbiR6WHRHq7wXl/n8guyh5AuBNQ3LIK44x0 KjGXP1FJkUhUuruGyZsMrDLBRHYi+hhDAgRjqHgoXi5XGETA1PAiNBNnQwMf5aubt+mE2Q5r qLNTgwSo2dpTU3+mJ3y3KlsIfoaxYI7XNsPRXGnZi4hbxmeb2NSXgdCXhX3nELUNYm4ArKBP LugOIT/zRwk0H0+RVwL2zHdMO1Tht1UOFGfOZpvuBF60jhMzbQARAQABtCxNYXhpbWUgQ29x dWVsaW4gPG1heGltZS5jb3F1ZWxpbkByZWRoYXQuY29tPokCOAQTAQIAIgUCV3u/5QIbAwYL CQgHAwIGFQgCCQoLBBYCAwECHgECF4AACgkQyjiNKEaHD4ma2g/+P+Hg9WkONPaY1J4AR7Uf kBneosS4NO3CRy0x4WYmUSLYMLx1I3VH6SVjqZ6uBoYy6Fs6TbF6SHNc7QbB6Qjo3neqnQR1 71Ua1MFvIob8vUEl3jAR/+oaE1UJKrxjWztpppQTukIk4oJOmXbL0nj3d8dA2QgHdTyttZ1H xzZJWWz6vqxCrUqHU7RSH9iWg9R2iuTzii4/vk1oi4Qz7y/q8ONOq6ffOy/t5xSZOMtZCspu Mll2Szzpc/trFO0pLH4LZZfz/nXh2uuUbk8qRIJBIjZH3ZQfACffgfNefLe2PxMqJZ8mFJXc RQO0ONZvwoOoHL6CcnFZp2i0P5ddduzwPdGsPq1bnIXnZqJSl3dUfh3xG5ArkliZ/++zGF1O wvpGvpIuOgLqjyCNNRoR7cP7y8F24gWE/HqJBXs1qzdj/5Hr68NVPV1Tu/l2D1KMOcL5sOrz 2jLXauqDWn1Okk9hkXAP7+0Cmi6QwAPuBT3i6t2e8UdtMtCE4sLesWS/XohnSFFscZR6Vaf3 gKdWiJ/fW64L6b9gjkWtHd4jAJBAIAx1JM6xcA1xMbAFsD8gA2oDBWogHGYcScY/4riDNKXi lw92d6IEHnSf6y7KJCKq8F+Jrj2BwRJiFKTJ6ChbOpyyR6nGTckzsLgday2KxBIyuh4w+hMq TGDSp2rmWGJjASq5Ag0EVPSbkwEQAMkaNc084Qvql+XW+wcUIY+Dn9A2D1gMr2BVwdSfVDN7 0ZYxo9PvSkzh6eQmnZNQtl8WSHl3VG3IEDQzsMQ2ftZn2sxjcCadexrQQv3Lu60Tgj7YVYRM H+fLYt9W5YuWduJ+FPLbjIKynBf6JCRMWr75QAOhhhaI0tsie3eDsKQBA0w7WCuPiZiheJaL 4MDe9hcH4rM3ybnRW7K2dLszWNhHVoYSFlZGYh+MGpuODeQKDS035+4H2rEWgg+iaOwqD7bg CQXwTZ1kSrm8NxIRVD3MBtzp9SZdUHLfmBl/tLVwDSZvHZhhvJHC6Lj6VL4jPXF5K2+Nn/Su CQmEBisOmwnXZhhu8ulAZ7S2tcl94DCo60ReheDoPBU8PR2TLg8rS5f9w6mLYarvQWL7cDtT d2eX3Z6TggfNINr/RTFrrAd7NHl5h3OnlXj7PQ1f0kfufduOeCQddJN4gsQfxo/qvWVB7PaE 1WTIggPmWS+Xxijk7xG6x9McTdmGhYaPZBpAxewK8ypl5+yubVsE9yOOhKMVo9DoVCjh5To5 aph7CQWfQsV7cd9PfSJjI2lXI0dhEXhQ7lRCFpf3V3mD6CyrhpcJpV6XVGjxJvGUale7+IOp sQIbPKUHpB2F+ZUPWds9yyVxGwDxD8WLqKKy0WLIjkkSsOb9UBNzgRyzrEC9lgQ/ABEBAAGJ Ah8EGAECAAkFAlT0m5MCGwwACgkQyjiNKEaHD4nU8hAAtt0xFJAy0sOWqSmyxTc7FUcX+pbD KVyPlpl6urKKMk1XtVMUPuae/+UwvIt0urk1mXi6DnrAN50TmQqvdjcPTQ6uoZ8zjgGeASZg jj0/bJGhgUr9U7oG7Hh2F8vzpOqZrdd65MRkxmc7bWj1k81tOU2woR/Gy8xLzi0k0KUa8ueB iYOcZcIGTcs9CssVwQjYaXRoeT65LJnTxYZif2pfNxfINFzCGw42s3EtZFteczClKcVSJ1+L +QUY/J24x0/ocQX/M1PwtZbB4c/2Pg/t5FS+s6UB1Ce08xsJDcwyOPIH6O3tccZuriHgvqKP yKz/Ble76+NFlTK1mpUlfM7PVhD5XzrDUEHWRTeTJSvJ8TIPL4uyfzhjHhlkCU0mw7Pscyxn DE8G0UYMEaNgaZap8dcGMYH/96EfE5s/nTX0M6MXV0yots7U2BDb4soLCxLOJz4tAFDtNFtA wLBhXRSvWhdBJZiig/9CG3dXmKfi2H+wdUCSvEFHRpgo7GK8/Kh3vGhgKmnnxhl8ACBaGy9n fxjSxjSO6rj4/MeenmlJw1yebzkX8ZmaSi8BHe+n6jTGEFNrbiOdWpJgc5yHIZZnwXaW54QT UhhSjDL1rV2B4F28w30jYmlRmm2RdN7iCZfbyP3dvFQTzQ4ySquuPkIGcOOHrvZzxbRjzMx1 Mwqu3GQ= Message-ID: <0605c461-d96a-0996-8dc4-b9097cdea9e6@redhat.com> Date: Fri, 18 Sep 2020 15:44:50 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200819032414.51430-5-yong.liu@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=maxime.coquelin@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Content-Language: en-US Subject: Re: [dpdk-dev] [PATCH v1 4/5] vhost: add packed ring vectorized dequeue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 8/19/20 5:24 AM, Marvin Liu wrote: > Optimize vhost packed ring dequeue path with SIMD instructions. Four > descriptors status check and writeback are batched handled with AVX512 > instructions. Address translation operations are also accelerated by > AVX512 instructions. > > If platform or compiler not support vectorization, will fallback to > default path. > > Signed-off-by: Marvin Liu > > diff --git a/lib/librte_vhost/Makefile b/lib/librte_vhost/Makefile > index 4f2f3e47da..c0cd7d498f 100644 > --- a/lib/librte_vhost/Makefile > +++ b/lib/librte_vhost/Makefile > @@ -31,6 +31,13 @@ CFLAGS += -DVHOST_ICC_UNROLL_PRAGMA > endif > endif > > +ifneq ($(FORCE_DISABLE_AVX512), y) > + CC_AVX512_SUPPORT=\ > + $(shell $(CC) -march=native -dM -E - &1 | \ > + sed '/./{H;$$!d} ; x ; /AVX512F/!d; /AVX512BW/!d; /AVX512VL/!d' | \ > + grep -q AVX512 && echo 1) > +endif > + > ifeq ($(CONFIG_RTE_LIBRTE_VHOST_NUMA),y) > LDLIBS += -lnuma > endif > @@ -40,6 +47,12 @@ LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf -lrte_ethdev -lrte_net > SRCS-$(CONFIG_RTE_LIBRTE_VHOST) := fd_man.c iotlb.c socket.c vhost.c \ > vhost_user.c virtio_net.c vdpa.c > > +ifeq ($(CC_AVX512_SUPPORT), 1) > +CFLAGS += -DCC_AVX512_SUPPORT > +SRCS-$(CONFIG_RTE_LIBRTE_VHOST) += vhost_vec_avx.c > +CFLAGS_vhost_vec_avx.o += -mavx512f -mavx512bw -mavx512vl > +endif > + > # install includes > SYMLINK-$(CONFIG_RTE_LIBRTE_VHOST)-include += rte_vhost.h rte_vdpa.h \ > rte_vdpa_dev.h rte_vhost_async.h > diff --git a/lib/librte_vhost/meson.build b/lib/librte_vhost/meson.build > index cc9aa65c67..c1481802d7 100644 > --- a/lib/librte_vhost/meson.build > +++ b/lib/librte_vhost/meson.build > @@ -8,6 +8,22 @@ endif > if has_libnuma == 1 > dpdk_conf.set10('RTE_LIBRTE_VHOST_NUMA', true) > endif > + > +if arch_subdir == 'x86' > + if not machine_args.contains('-mno-avx512f') > + if cc.has_argument('-mavx512f') and cc.has_argument('-mavx512vl') and cc.has_argument('-mavx512bw') > + cflags += ['-DCC_AVX512_SUPPORT'] > + vhost_avx512_lib = static_library('vhost_avx512_lib', > + 'vhost_vec_avx.c', > + dependencies: [static_rte_eal, static_rte_mempool, > + static_rte_mbuf, static_rte_ethdev, static_rte_net], > + include_directories: includes, > + c_args: [cflags, '-mavx512f', '-mavx512bw', '-mavx512vl']) > + objs += vhost_avx512_lib.extract_objects('vhost_vec_avx.c') > + endif > + endif > +endif > + > if (toolchain == 'gcc' and cc.version().version_compare('>=8.3.0')) > cflags += '-DVHOST_GCC_UNROLL_PRAGMA' > elif (toolchain == 'clang' and cc.version().version_compare('>=3.7.0')) > diff --git a/lib/librte_vhost/vhost.h b/lib/librte_vhost/vhost.h > index 4a81f18f01..fc7daf2145 100644 > --- a/lib/librte_vhost/vhost.h > +++ b/lib/librte_vhost/vhost.h > @@ -1124,4 +1124,12 @@ virtio_dev_pktmbuf_alloc(struct virtio_net *dev, struct rte_mempool *mp, > return NULL; > } > > +int > +vhost_reserve_avail_batch_packed_avx(struct virtio_net *dev, > + struct vhost_virtqueue *vq, > + struct rte_mempool *mbuf_pool, > + struct rte_mbuf **pkts, > + uint16_t avail_idx, > + uintptr_t *desc_addrs, > + uint16_t *ids); > #endif /* _VHOST_NET_CDEV_H_ */ > diff --git a/lib/librte_vhost/vhost_vec_avx.c b/lib/librte_vhost/vhost_vec_avx.c > new file mode 100644 > index 0000000000..e8361d18fa > --- /dev/null > +++ b/lib/librte_vhost/vhost_vec_avx.c > @@ -0,0 +1,152 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2010-2016 Intel Corporation > + */ > +#include > + > +#include "vhost.h" > + > +#define BYTE_SIZE 8 > +/* reference count offset in mbuf rearm data */ > +#define REFCNT_BITS_OFFSET ((offsetof(struct rte_mbuf, refcnt) - \ > + offsetof(struct rte_mbuf, rearm_data)) * BYTE_SIZE) > +/* segment number offset in mbuf rearm data */ > +#define SEG_NUM_BITS_OFFSET ((offsetof(struct rte_mbuf, nb_segs) - \ > + offsetof(struct rte_mbuf, rearm_data)) * BYTE_SIZE) > + > +/* default rearm data */ > +#define DEFAULT_REARM_DATA (1ULL << SEG_NUM_BITS_OFFSET | \ > + 1ULL << REFCNT_BITS_OFFSET) > + > +#define DESC_FLAGS_SHORT_OFFSET (offsetof(struct vring_packed_desc, flags) / \ > + sizeof(uint16_t)) > + > +#define DESC_FLAGS_SHORT_SIZE (sizeof(struct vring_packed_desc) / \ > + sizeof(uint16_t)) > +#define BATCH_FLAGS_MASK (1 << DESC_FLAGS_SHORT_OFFSET | \ > + 1 << (DESC_FLAGS_SHORT_OFFSET + DESC_FLAGS_SHORT_SIZE) | \ > + 1 << (DESC_FLAGS_SHORT_OFFSET + DESC_FLAGS_SHORT_SIZE * 2) | \ > + 1 << (DESC_FLAGS_SHORT_OFFSET + DESC_FLAGS_SHORT_SIZE * 3)) > + > +#define FLAGS_BITS_OFFSET ((offsetof(struct vring_packed_desc, flags) - \ > + offsetof(struct vring_packed_desc, len)) * BYTE_SIZE) > + > +#define PACKED_FLAGS_MASK ((0ULL | VRING_DESC_F_AVAIL | VRING_DESC_F_USED) \ > + << FLAGS_BITS_OFFSET) > +#define PACKED_AVAIL_FLAG ((0ULL | VRING_DESC_F_AVAIL) << FLAGS_BITS_OFFSET) > +#define PACKED_AVAIL_FLAG_WRAP ((0ULL | VRING_DESC_F_USED) << \ > + FLAGS_BITS_OFFSET) > + > +#define DESC_FLAGS_POS 0xaa > +#define MBUF_LENS_POS 0x6666 > + > +int > +vhost_reserve_avail_batch_packed_avx(struct virtio_net *dev, > + struct vhost_virtqueue *vq, > + struct rte_mempool *mbuf_pool, > + struct rte_mbuf **pkts, > + uint16_t avail_idx, > + uintptr_t *desc_addrs, > + uint16_t *ids) > +{ > + struct vring_packed_desc *descs = vq->desc_packed; > + uint32_t descs_status; > + void *desc_addr; > + uint16_t i; > + uint8_t cmp_low, cmp_high, cmp_result; > + uint64_t lens[PACKED_BATCH_SIZE]; > + > + if (unlikely(avail_idx & PACKED_BATCH_MASK)) > + return -1; > + > + /* load 4 descs */ > + desc_addr = &vq->desc_packed[avail_idx]; > + __m512i desc_vec = _mm512_loadu_si512(desc_addr); > + > + /* burst check four status */ > + __m512i avail_flag_vec; > + if (vq->avail_wrap_counter) > +#if defined(RTE_ARCH_I686) > + avail_flag_vec = _mm512_set4_epi64(PACKED_AVAIL_FLAG, 0x0, > + PACKED_FLAGS_MASK, 0x0); > +#else > + avail_flag_vec = _mm512_maskz_set1_epi64(DESC_FLAGS_POS, > + PACKED_AVAIL_FLAG); > + > +#endif > + else > +#if defined(RTE_ARCH_I686) > + avail_flag_vec = _mm512_set4_epi64(PACKED_AVAIL_FLAG_WRAP, > + 0x0, PACKED_AVAIL_FLAG_WRAP, 0x0); > +#else > + avail_flag_vec = _mm512_maskz_set1_epi64(DESC_FLAGS_POS, > + PACKED_AVAIL_FLAG_WRAP); > +#endif > + > + descs_status = _mm512_cmp_epu16_mask(desc_vec, avail_flag_vec, > + _MM_CMPINT_NE); > + if (descs_status & BATCH_FLAGS_MASK) > + return -1; > + > + /* check buffer fit into one region & translate address */ > + __m512i regions_low_addrs = > + _mm512_loadu_si512((void *)&dev->regions_low_addrs); > + __m512i regions_high_addrs = > + _mm512_loadu_si512((void *)&dev->regions_high_addrs); > + vhost_for_each_try_unroll(i, 0, PACKED_BATCH_SIZE) { > + uint64_t addr_low = descs[avail_idx + i].addr; > + uint64_t addr_high = addr_low + descs[avail_idx + i].len; > + __m512i low_addr_vec = _mm512_set1_epi64(addr_low); > + __m512i high_addr_vec = _mm512_set1_epi64(addr_high); > + > + cmp_low = _mm512_cmp_epi64_mask(low_addr_vec, > + regions_low_addrs, _MM_CMPINT_NLT); > + cmp_high = _mm512_cmp_epi64_mask(high_addr_vec, > + regions_high_addrs, _MM_CMPINT_LT); > + cmp_result = cmp_low & cmp_high; > + int index = __builtin_ctz(cmp_result); > + if (unlikely((uint32_t)index >= dev->mem->nregions)) > + goto free_buf; > + > + desc_addrs[i] = addr_low + > + dev->mem->regions[index].host_user_addr - > + dev->mem->regions[index].guest_phys_addr; > + lens[i] = descs[avail_idx + i].len; > + rte_prefetch0((void *)(uintptr_t)desc_addrs[i]); > + > + pkts[i] = virtio_dev_pktmbuf_alloc(dev, mbuf_pool, lens[i]); > + if (!pkts[i]) > + goto free_buf; > + } The above does not support vIOMMU, isn't it? The more the packed datapath evolves, the more it gets optimized for a very specific configuration. In v19.11, indirect descriptors and chained buffers are handled as a fallback. And now vIOMMU support is handled as a fallback. I personnally don't like the path it is taking as it is adding a lot of complexity on top of that.