From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
To: Stanislaw Kardach <kda@semihalf.com>
Cc: Frank Zhao <Frank.Zhao@starfivetech.com>,
Sam Grove <sam.grove@sifive.com>,
mw@semihalf.com, upstream@semihalf.com, dev@dpdk.org
Subject: Re: [PATCH 00/11] Introduce support for RISC-V architecture
Date: Thu, 12 May 2022 10:04:05 +0200 [thread overview]
Message-ID: <07665f47-a437-d1df-d613-e01062a6668c@canonical.com> (raw)
In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com>
On 5/5/22 19:29, Stanislaw Kardach wrote:
> This patchset adds support for building and running DPDK on 64bit RISC-V
> architecture. The initial support targets rv64gc (rv64imafdc) ISA and
> was tested on SiFive Unmatched development board with the Freedom U740
> SoC running Linux (freedom-u-sdk based kernel).
> I have tested this codebase using DPDK unit and perf tests as well as
> test-pmd, l2fwd and l3fwd examples.
> The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
> On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
> uio_pci_generic and vfio-pci noiommu drivers.
>
> Commits 1-2 fix small issues which are encountered if a given platform
> does not support any vector operations (which is the case with U740).
> Commit 3 introduces EAL and build system support for RISC-V architecture
> as well as documentation updates.
> Commits 4-7 add missing defines and stubs to enable RISC-V operation in
> non-EAL parts.
> Commit 8 adds RISC-V specific cpuflags test.
> Commit 9 works around a bug in the current GCC in test_ring compiled
> with -O0 or -Og.
> Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
> iterating over cross-compile config files (currently present for
> generic rv64gc and SiFive U740).
> Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
> measurements. This is an extraneous commit which is not directly
> needed for RISC-V support but was noticed when we have started
> gathering test results. If needed, I can submit it separately.
>
> I appreciate Your comments and feedback.
>
> Best Regards,
> Stanislaw Kardach
On an SiFive Unmatched board with Ubuntu Jammy I have been compiling
DPDK origin/main (36db4a1ad464) with this series and the test patches
that you split off.
The fast tests are either skipped or succeed. But I have seen errors for
the performance tests:
4 1GiB hugepages defined
no network devices bound
vfio_pci loaded (no IOMMU)
sudo meson -t 30
129/173 DPDK:perf-tests / pmd_perf_autotest FAIL 7.85s (exit status 255
or signal 127 SIGinvalid)
>>> DPDK_TEST=pmd_perf_autotest MALLOC_PERTURB_=135
build/app/test/dpdk-test
136/173 DPDK:perf-tests / ipsec_perf_autotest FAIL 4.47s (exit status
255 or signal 127 SIGinvalid)
>>> MALLOC_PERTURB_=181 DPDK_TEST=ipsec_perf_autotest
build/app/test/dpdk-test
160/173 DPDK:driver-tests / link_bonding_mode4_autotest FAIL 31.80s
killed by signal 11 SIGSEGV
>>> MALLOC_PERTURB_=62 DPDK_TEST=link_bonding_mode4_autotest
build/app/test/dpdk-test
These are the patches used:
# [PATCH 1/1] lpm: add a scalar version of lookupx4 function
https://inbox.dpdk.org/dev/20220510115824.457885-1-kda@semihalf.com/
# [PATCH 1/1] examples/l3fwd: fix scalar LPM compilation
https://inbox.dpdk.org/dev/20220510115844.458009-1-kda@semihalf.com/
# [PATCH 1/1] test/hash: report non HTM numbers for single r/w
https://inbox.dpdk.org/dev/20220510115734.457718-1-kda@semihalf.com/
# [PATCH 1/1] test/ring: remove excessive inlining
https://inbox.dpdk.org/dev/20220510115758.457794-1-kda@semihalf.com/
# [PATCH v3 0/8] Introduce support for RISC-V architecture
https://inbox.dpdk.org/dev/20220510154849.530872-1-kda@semihalf.com/
# [PATCH 1/1] drivers: define OPENSSL_API_COMPAT
https://inbox.dpdk.org/dev/20220510150635.61975-1-heinrich.schuchardt@canonical.com/
Running sudo app/test/dpdk-test does not show the errors:
RTE>>pmd_perf_autotest
Start PMD RXTX cycles cost test.
At least 1 port(s) used for perf. test
Test Failed
RTE>>ipsec_perf_autotest
USER1: rte_ipsec_pkt_crypto_prepare fail
Test Failed
RTE>>link_bonding_mode4_autotest
...
Test OK
RTE>
Best regards
Heinrich
>
> NOTE: This work was sponsored by StarFive and SiFive which is signified by
> "Sponsored-by:" sign-offs in each commit message. After discussing it
> with Thomas Monjalon it seemed a better choice than "Suggested-by" which
> does not fully convey the nature of involvement. However it makes
> Linux checkpatch unhappy so I'm not sure if I shouldn't change the
> sign-offs.
>
> NOTE2: I have added maintainers for each commit based on MAINTAINERS file.
> However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
> any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
> if it was a commit adding new files.
>
> Michal Mazurek (3):
> lpm: add a scalar version of lookupx4 function
> eal: add initial support for RISC-V architecture
> test/cpuflags: add test for RISC-V cpu flag
>
> Stanislaw Kardach (8):
> examples/l3fwd: fix scalar LPM compilation
> net/ixgbe: enable vector stubs for RISC-V
> net/memif: set memfd syscall ID on RISC-V
> net/tap: set BPF syscall ID for RISC-V
> examples/l3fwd: enable RISC-V operation
> test/ring: disable problematic tests for RISC-V
> devtools: add RISC-V to test-meson-builds.sh
> test/hash: report non HTM numbers for single r/w
>
> MAINTAINERS | 6 +
> app/test/test_cpuflags.c | 81 ++++++++++
> app/test/test_hash_readwrite.c | 8 +-
> app/test/test_ring.c | 8 +
> app/test/test_xmmt_ops.h | 16 ++
> config/meson.build | 2 +
> config/riscv/meson.build | 148 ++++++++++++++++++
> config/riscv/riscv64_linux_gcc | 17 ++
> config/riscv/riscv64_sifive_u740_linux_gcc | 19 +++
> devtools/test-meson-builds.sh | 6 +
> doc/guides/contributing/design.rst | 2 +-
> .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++++++++++++++
> doc/guides/linux_gsg/index.rst | 1 +
> doc/guides/nics/features.rst | 5 +
> doc/guides/nics/features/default.ini | 1 +
> doc/guides/nics/features/ixgbe.ini | 1 +
> doc/guides/rel_notes/release_22_07.rst | 29 ++++
> drivers/net/i40e/meson.build | 6 +
> drivers/net/ixgbe/ixgbe_rxtx.c | 4 +-
> drivers/net/memif/rte_eth_memif.h | 2 +
> drivers/net/tap/tap_bpf.h | 2 +
> examples/l3fwd/l3fwd_em.c | 8 +
> examples/l3fwd/l3fwd_fib.c | 2 +
> examples/l3fwd/l3fwd_lpm.c | 2 +-
> lib/eal/riscv/include/meson.build | 23 +++
> lib/eal/riscv/include/rte_atomic.h | 52 ++++++
> lib/eal/riscv/include/rte_byteorder.h | 44 ++++++
> lib/eal/riscv/include/rte_cpuflags.h | 55 +++++++
> lib/eal/riscv/include/rte_cycles.h | 103 ++++++++++++
> lib/eal/riscv/include/rte_io.h | 21 +++
> lib/eal/riscv/include/rte_mcslock.h | 18 +++
> lib/eal/riscv/include/rte_memcpy.h | 63 ++++++++
> lib/eal/riscv/include/rte_pause.h | 31 ++++
> lib/eal/riscv/include/rte_pflock.h | 17 ++
> lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++
> lib/eal/riscv/include/rte_prefetch.h | 50 ++++++
> lib/eal/riscv/include/rte_rwlock.h | 44 ++++++
> lib/eal/riscv/include/rte_spinlock.h | 67 ++++++++
> lib/eal/riscv/include/rte_ticketlock.h | 21 +++
> lib/eal/riscv/include/rte_vect.h | 55 +++++++
> lib/eal/riscv/meson.build | 11 ++
> lib/eal/riscv/rte_cpuflags.c | 122 +++++++++++++++
> lib/eal/riscv/rte_cycles.c | 77 +++++++++
> lib/eal/riscv/rte_hypervisor.c | 13 ++
> lib/eal/riscv/rte_power_intrinsics.c | 56 +++++++
> lib/lpm/meson.build | 1 +
> lib/lpm/rte_lpm.h | 4 +-
> lib/lpm/rte_lpm_scalar.h | 122 +++++++++++++++
> meson.build | 2 +
> 49 files changed, 1588 insertions(+), 7 deletions(-)
> create mode 100644 config/riscv/meson.build
> create mode 100644 config/riscv/riscv64_linux_gcc
> create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
> create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> create mode 100644 lib/eal/riscv/include/meson.build
> create mode 100644 lib/eal/riscv/include/rte_atomic.h
> create mode 100644 lib/eal/riscv/include/rte_byteorder.h
> create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
> create mode 100644 lib/eal/riscv/include/rte_cycles.h
> create mode 100644 lib/eal/riscv/include/rte_io.h
> create mode 100644 lib/eal/riscv/include/rte_mcslock.h
> create mode 100644 lib/eal/riscv/include/rte_memcpy.h
> create mode 100644 lib/eal/riscv/include/rte_pause.h
> create mode 100644 lib/eal/riscv/include/rte_pflock.h
> create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
> create mode 100644 lib/eal/riscv/include/rte_prefetch.h
> create mode 100644 lib/eal/riscv/include/rte_rwlock.h
> create mode 100644 lib/eal/riscv/include/rte_spinlock.h
> create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
> create mode 100644 lib/eal/riscv/include/rte_vect.h
> create mode 100644 lib/eal/riscv/meson.build
> create mode 100644 lib/eal/riscv/rte_cpuflags.c
> create mode 100644 lib/eal/riscv/rte_cycles.c
> create mode 100644 lib/eal/riscv/rte_hypervisor.c
> create mode 100644 lib/eal/riscv/rte_power_intrinsics.c
> create mode 100644 lib/lpm/rte_lpm_scalar.h
>
next prev parent reply other threads:[~2022-05-12 8:04 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 17:29 Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 01/11] lpm: add a scalar version of lookupx4 function Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Stanislaw Kardach
2022-05-05 17:39 ` Stephen Hemminger
2022-05-05 17:49 ` Stanisław Kardach
2022-05-05 18:09 ` Stephen Hemminger
2022-05-05 17:29 ` [PATCH 03/11] eal: add initial support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 07/11] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 09/11] test/ring: disable problematic tests for RISC-V Stanislaw Kardach
2022-05-05 17:35 ` Stephen Hemminger
2022-05-05 17:43 ` Stanisław Kardach
2022-05-05 18:06 ` Stephen Hemminger
2022-05-10 23:28 ` Honnappa Nagarahalli
2022-05-11 10:07 ` Stanisław Kardach
2022-05-05 17:30 ` [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 11/11] test/hash: report non HTM numbers for single r/w Stanislaw Kardach
2022-05-06 9:13 ` [PATCH 00/11] Introduce support for RISC-V architecture David Marchand
2022-05-09 12:24 ` Stanisław Kardach
2022-05-09 12:30 ` Thomas Monjalon
2022-05-11 8:09 ` Morten Brørup
2022-05-11 10:28 ` Stanisław Kardach
2022-05-11 11:06 ` Thomas Monjalon
2022-05-09 14:30 ` David Marchand
2022-05-10 11:21 ` Stanisław Kardach
2022-05-10 12:31 ` Thomas Monjalon
2022-05-10 14:00 ` Stanisław Kardach
2022-05-10 14:23 ` Thomas Monjalon
2022-05-10 15:07 ` [PATCH v2 0/8] " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 1/8] eal: add initial " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:35 ` Stanisław Kardach
2022-05-10 15:07 ` [PATCH v2 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 0/8] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 1/8] eal: add initial " Stanislaw Kardach
2022-05-13 6:50 ` Heinrich Schuchardt
2022-05-13 8:42 ` Stanisław Kardach
2022-05-13 10:51 ` Heinrich Schuchardt
2022-05-13 11:47 ` Stanisław Kardach
2022-05-13 15:37 ` Stephen Hemminger
2022-05-16 8:00 ` Stanisław Kardach
2022-05-10 15:48 ` [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-12 15:47 ` Aaron Conole
2022-05-12 16:07 ` Stanisław Kardach
2022-05-13 14:33 ` Aaron Conole
2022-05-12 8:04 ` Heinrich Schuchardt [this message]
2022-05-12 8:35 ` [PATCH 00/11] Introduce support for RISC-V architecture Stanisław Kardach
2022-05-12 9:46 ` Heinrich Schuchardt
2022-05-12 13:56 ` Stanisław Kardach
2022-05-12 21:06 ` Heinrich Schuchardt
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