From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AEE6843D75; Fri, 29 Mar 2024 04:25:14 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7ADE240268; Fri, 29 Mar 2024 04:25:14 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 0F82340042 for <dev@dpdk.org>; Fri, 29 Mar 2024 04:25:12 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4V5Qh51L5Xz1R85v; Fri, 29 Mar 2024 11:22:29 +0800 (CST) Received: from kwepemm600004.china.huawei.com (unknown [7.193.23.242]) by mail.maildlp.com (Postfix) with ESMTPS id 872451400D6; Fri, 29 Mar 2024 11:25:10 +0800 (CST) Received: from [10.67.121.59] (10.67.121.59) by kwepemm600004.china.huawei.com (7.193.23.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 29 Mar 2024 11:25:09 +0800 Message-ID: <084e48f7-b67d-32be-3c01-e7a582b9e15b@huawei.com> Date: Fri, 29 Mar 2024 11:25:09 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH v2 1/6] ethdev: support setting lanes To: Ajit Khaparde <ajit.khaparde@broadcom.com> CC: Thomas Monjalon <thomas@monjalon.net>, huangdengdui <huangdengdui@huawei.com>, Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>, <roretzla@linux.microsoft.com>, <dev@dpdk.org>, <ferruh.yigit@amd.com>, <aman.deep.singh@intel.com>, <yuying.zhang@intel.com>, <andrew.rybchenko@oktetlabs.ru>, <stephen@networkplumber.org>, <jerinjacobk@gmail.com>, <liuyonglong@huawei.com>, <fengchengwen@huawei.com>, <haijie1@huawei.com> References: <20240312075238.3319480-4-huangdengdui@huawei.com> <3325989.AxlXzFCzgd@thomas> <68ee0a54-c0b4-293c-67ee-efed8964c33b@huawei.com> <3628913.0YcMNavOfZ@thomas> <baa88ae9-ee13-8a9b-839b-d4e50c52b1f8@huawei.com> <CACZ4nhsKMwdfGhbMELthybKWiAWd7gGscTjYQCc-SzNHe8nr_w@mail.gmail.com> From: "lihuisong (C)" <lihuisong@huawei.com> In-Reply-To: <CACZ4nhsKMwdfGhbMELthybKWiAWd7gGscTjYQCc-SzNHe8nr_w@mail.gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.121.59] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemm600004.china.huawei.com (7.193.23.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org 在 2024/3/26 21:47, Ajit Khaparde 写道: > On Tue, Mar 26, 2024 at 4:15 AM lihuisong (C) <lihuisong@huawei.com> wrote: >> >> 在 2024/3/26 18:30, Thomas Monjalon 写道: >>> 26/03/2024 02:42, lihuisong (C): >>>> 在 2024/3/25 17:30, Thomas Monjalon 写道: >>>>> 25/03/2024 07:24, huangdengdui: >>>>>> On 2024/3/22 21:58, Thomas Monjalon wrote: >>>>>>> 22/03/2024 08:09, Dengdui Huang: >>>>>>>> -#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps */ >>>>>>>> -#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps 2lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps 4lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps 4lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps 4lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps 4lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_10G_4LANES RTE_BIT32(17) /**< 10 Gbps 4lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_50G_2LANES RTE_BIT32(18) /**< 50 Gbps 2 lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_100G_2LANES RTE_BIT32(19) /**< 100 Gbps 2 lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_100G_4LANES RTE_BIT32(20) /**< 100 Gbps 4lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_200G_2LANES RTE_BIT32(21) /**< 200 Gbps 2lanes */ >>>>>>>> +#define RTE_ETH_LINK_SPEED_400G_8LANES RTE_BIT32(22) /**< 400 Gbps 8lanes */ >>>>>>> I don't think it is a good idea to make this more complex. >>>>>>> It brings nothing as far as I can see, compared to having speed and lanes separated. >>>>>>> Can we have lanes information a separate value? no need for bitmask. >>>>>>> >>>>>> Hi,Thomas, Ajit, roretzla, damodharam >>>>>> >>>>>> I also considered the option at the beginning of the design. >>>>>> But this option is not used due to the following reasons: >>>>>> 1. For the user, ethtool couples speed and lanes. >>>>>> The result of querying the NIC capability is as follows: >>>>>> Supported link modes: >>>>>> 100000baseSR4/Full >>>>>> 100000baseSR2/Full >>>>>> The NIC capability is configured as follows: >>>>>> ethtool -s eth1 speed 100000 lanes 4 autoneg off >>>>>> ethtool -s eth1 speed 100000 lanes 2 autoneg off >>>>>> >>>>>> Therefore, users are more accustomed to the coupling of speed and lanes. >>>>>> >>>>>> 2. For the PHY, When the physical layer capability is configured through the MDIO, >>>>>> the speed and lanes are also coupled. >>>>>> For example: >>>>>> Table 45–7—PMA/PMD control 2 register bit definitions[1] >>>>>> PMA/PMD type selection >>>>>> 1 0 0 1 0 1 0 = 100GBASE-SR2 PMA/PMD >>>>>> 0 1 0 1 1 1 1 = 100GBASE-SR4 PMA/PMD >>>>>> >>>>>> Therefore, coupling speeds and lanes is easier to understand. >>>>>> And it is easier for the driver to report the support lanes. >>>>>> >>>>>> In addition, the code implementation is compatible with the old version. >>>>>> When the driver does not support the lanes setting, the code does not need to be modified. >>>>>> >>>>>> So I think the speed and lanes coupling is better. >>>>> I don't think so. >>>>> You are mixing hardware implementation, user tool, and API. >>>>> Having a separate and simple API is cleaner and not more difficult to handle >>>>> in some get/set style functions. >>>> Having a separate and simple API is cleaner. It's good. >>>> But supported lane capabilities have a lot to do with the specified >>>> speed. This is determined by releated specification. >>>> If we add a separate API for speed lanes, it probably is hard to check >>>> the validity of the configuration for speed and lanes. >>>> And the setting lane API sepparated from speed is not good for >>>> uniforming all PMD's behavior in ethdev layer. >>> Please let's be more specific. >>> There are 3 needs: >>> - set PHY lane config >>> - get PHY lane config >>> - get PHY lane capabilities >> IMO, this lane capabilities should be reported based on supported speed >> capabilities. >>> There is no problem providing a function to get the number of PHY lanes. >>> It is possible to set PHY lanes number after defining a fixed speed. >> yes it's ok. >>>> The patch[1] is an example for this separate API. >>>> I think it is not very good. It cannot tell user and PMD the follow points: >>>> 1) user don't know what lanes should or can be set for a specified speed >>>> on one NIC. >>> This is about capabilities. >>> Can we say a HW will support a maximum number of PHY lanes in general? >>> We may need to associate the maximum speed per lane? >>> Do we really need to associate PHY lane and PHY speed numbers for capabilities? >> Personally, it should contain the below releationship at least. >> speed 10G --> 1lane | 4lane >> speed 100G --> 2lane | 4lane >>> Example: if a HW supports 100G-4-lanes and 200G-2-lanes, >>> may we assume it is also supporting 200G-4-lanes? >> I think we cannot assume that NIC also support 200G-4-lanes. >> Beause it has a lot to do with HW design. >>>> 2) how should PMD do for a supported lanes in their HW? >>> I don't understand this question. Please rephrase. >> I mean that PMD don't know set how many lanes when the lanes from user >> is not supported on a fixed speed by PMD. >> So ethdev layer should limit the avaiable lane number based on a fixed >> speed. > ethdev layer has generally been opaque. We should keep it that way. > The PMD should know what the HW supports. If one operation is common for all PMD, which is recommanded to do it in ethdev layer. > So it should show the capabilities correctly. Right? Yes, the lane capabilities of differrent speed are necessary for user. > And if the user provides incorrect settings, it should reject it. Rejecting it in this case is no any reason. > >>>> Anyway, if we add setting speed lanes feature, we must report and set >>>> speed and lanes capabilities for user well. >>>> otherwise, user will be more confused. >>> Well is not necessarily exposing all raw combinations as ethtool does. >> Agreed. >>>> [1] https://patchwork.dpdk.org/project/dpdk/list/?series=31606 >>> >>> .