From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E7DEA00BE; Thu, 16 Jun 2022 12:30:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B95FE410E8; Thu, 16 Jun 2022 12:30:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1E4224003C for ; Thu, 16 Jun 2022 12:30:23 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25G9GHOw011985 for ; Thu, 16 Jun 2022 03:30:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pfpt0220; bh=LQTP8aaaBFlOpoMJw1GLjbKjDqopFzPMUzPY6isomWI=; b=aagOl77pm+WB3jKrot14jdyLbabTOH/SjOfi0vZSy60GK0B4SHWmtZDDxcspR2PZSbvk ecq2Vomx4VRZHIcRZ1CPMJduNrajNhub6qEvYIoVuwS8r38recUjKQlMOZalBqBsPHVA I/fW/l7WBcxJMTBluECBteNAL/AOkKFnfxMZ36A8hrhktIPtiY6B8RNufOmSE5xIHj7D XjzkDGJdaqSTIJsHbRqV6jM1njWb5kDaqdkHmOfg+IXvnfG9RasRlYQuExjQ8op5CQyq /GSFzFBgA3Ny/0clYzoyVRcvRpy7nQIcFZViUvIuRlvArzgA8yv9iuEeQA9bb61EOPDk oA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gr1qvra0u-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Jun 2022 03:30:22 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 16 Jun 2022 03:30:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Jun 2022 03:30:20 -0700 Received: from [10.28.175.194] (unknown [10.28.175.194]) by maili.marvell.com (Postfix) with ESMTP id E274C3F709B; Thu, 16 Jun 2022 03:30:18 -0700 (PDT) Message-ID: <0883f9c9-d36d-2adc-539a-68b414db5bcd@marvell.com> Date: Thu, 16 Jun 2022 16:00:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v2 12/12] event/cnxk: offset timestamp data only if enabled on port Content-Language: en-US To: , Pavan Nikhilesh , "Shijith Thotton" CC: , , References: <20220616070743.30658-1-ndabilpuram@marvell.com> <20220616092420.17861-1-ndabilpuram@marvell.com> <20220616092420.17861-12-ndabilpuram@marvell.com> From: Nithin Kumar Dabilpuram In-Reply-To: <20220616092420.17861-12-ndabilpuram@marvell.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: fyeH7-x1jgkcdhzgCk1Vp38iCcnND47- X-Proofpoint-GUID: fyeH7-x1jgkcdhzgCk1Vp38iCcnND47- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-16_06,2022-06-16_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Please ignore this particular patch 12/12. It is already part of other patch. https://patchwork.dpdk.org/project/dpdk/patch/20220612175612.3101-1-pbhagavatula@marvell.com/ Thanks Nithin On 2022-06-16 2:54 PM, Nithin Dabilpuram wrote: > Offset timestamp data only when enabled on the port instead of > just checking for offload flags. > > Signed-off-by: Nithin Dabilpuram > --- > drivers/event/cnxk/cn10k_worker.h | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h > index 034f508..7412a1b 100644 > --- a/drivers/event/cnxk/cn10k_worker.h > +++ b/drivers/event/cnxk/cn10k_worker.h > @@ -112,8 +112,7 @@ static __rte_always_inline void > cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, > void *lookup_mem, void *tstamp, uintptr_t lbase) > { > - uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM | > - (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0); > + uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM; > struct rte_event_vector *vec; > uint64_t aura_handle, laddr; > uint16_t nb_mbufs, non_vec; > @@ -133,6 +132,9 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, > for (i = OBJS_PER_CLINE; i < vec->nb_elem; i += OBJS_PER_CLINE) > rte_prefetch0(&vec->ptrs[i]); > > + if (flags & NIX_RX_OFFLOAD_TSTAMP_F && tstamp) > + mbuf_init |= 8; > + > nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP); > nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs, > flags | NIX_RX_VWQE_F, lookup_mem,