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From: Anatoly Burakov <anatoly.burakov@intel.com>
To: dev@dpdk.org
Cc: ian.stokes@intel.com, bruce.richardson@intel.com,
Lukasz Plachno <lukasz.plachno@intel.com>
Subject: [PATCH v2 116/148] net/ice/base: replace array initialization with
macros
Date: Wed, 12 Jun 2024 16:01:50 +0100
Message-ID: <0935df14244ac154eae3fadddd27ff64018dff77.1718204529.git.anatoly.burakov@intel.com>
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Certain compilers do not allow array initialization with indexes, so
the best way to avoid the issue when compiling for these platforms is
to use a macro.
Signed-off-by: Lukasz Plachno <lukasz.plachno@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
drivers/net/ice/base/ice_common.c | 86 +++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 8 +++
2 files changed, 94 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 94f17a244f..e94bec26a8 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -12,6 +12,92 @@
#define ICE_PF_RESET_WAIT_COUNT 300
+static const char * const ice_link_mode_str_low[] = {
+ ice_arr_elem_idx(0, "100BASE_TX"),
+ ice_arr_elem_idx(1, "100M_SGMII"),
+ ice_arr_elem_idx(2, "1000BASE_T"),
+ ice_arr_elem_idx(3, "1000BASE_SX"),
+ ice_arr_elem_idx(4, "1000BASE_LX"),
+ ice_arr_elem_idx(5, "1000BASE_KX"),
+ ice_arr_elem_idx(6, "1G_SGMII"),
+ ice_arr_elem_idx(7, "2500BASE_T"),
+ ice_arr_elem_idx(8, "2500BASE_X"),
+ ice_arr_elem_idx(9, "2500BASE_KX"),
+ ice_arr_elem_idx(10, "5GBASE_T"),
+ ice_arr_elem_idx(11, "5GBASE_KR"),
+ ice_arr_elem_idx(12, "10GBASE_T"),
+ ice_arr_elem_idx(13, "10G_SFI_DA"),
+ ice_arr_elem_idx(14, "10GBASE_SR"),
+ ice_arr_elem_idx(15, "10GBASE_LR"),
+ ice_arr_elem_idx(16, "10GBASE_KR_CR1"),
+ ice_arr_elem_idx(17, "10G_SFI_AOC_ACC"),
+ ice_arr_elem_idx(18, "10G_SFI_C2C"),
+ ice_arr_elem_idx(19, "25GBASE_T"),
+ ice_arr_elem_idx(20, "25GBASE_CR"),
+ ice_arr_elem_idx(21, "25GBASE_CR_S"),
+ ice_arr_elem_idx(22, "25GBASE_CR1"),
+ ice_arr_elem_idx(23, "25GBASE_SR"),
+ ice_arr_elem_idx(24, "25GBASE_LR"),
+ ice_arr_elem_idx(25, "25GBASE_KR"),
+ ice_arr_elem_idx(26, "25GBASE_KR_S"),
+ ice_arr_elem_idx(27, "25GBASE_KR1"),
+ ice_arr_elem_idx(28, "25G_AUI_AOC_ACC"),
+ ice_arr_elem_idx(29, "25G_AUI_C2C"),
+ ice_arr_elem_idx(30, "40GBASE_CR4"),
+ ice_arr_elem_idx(31, "40GBASE_SR4"),
+ ice_arr_elem_idx(32, "40GBASE_LR4"),
+ ice_arr_elem_idx(33, "40GBASE_KR4"),
+ ice_arr_elem_idx(34, "40G_XLAUI_AOC_ACC"),
+ ice_arr_elem_idx(35, "40G_XLAUI"),
+ ice_arr_elem_idx(36, "50GBASE_CR2"),
+ ice_arr_elem_idx(37, "50GBASE_SR2"),
+ ice_arr_elem_idx(38, "50GBASE_LR2"),
+ ice_arr_elem_idx(39, "50GBASE_KR2"),
+ ice_arr_elem_idx(40, "50G_LAUI2_AOC_ACC"),
+ ice_arr_elem_idx(41, "50G_LAUI2"),
+ ice_arr_elem_idx(42, "50G_AUI2_AOC_ACC"),
+ ice_arr_elem_idx(43, "50G_AUI2"),
+ ice_arr_elem_idx(44, "50GBASE_CP"),
+ ice_arr_elem_idx(45, "50GBASE_SR"),
+ ice_arr_elem_idx(46, "50GBASE_FR"),
+ ice_arr_elem_idx(47, "50GBASE_LR"),
+ ice_arr_elem_idx(48, "50GBASE_KR_PAM4"),
+ ice_arr_elem_idx(49, "50G_AUI1_AOC_ACC"),
+ ice_arr_elem_idx(50, "50G_AUI1"),
+ ice_arr_elem_idx(51, "100GBASE_CR4"),
+ ice_arr_elem_idx(52, "100GBASE_SR4"),
+ ice_arr_elem_idx(53, "100GBASE_LR4"),
+ ice_arr_elem_idx(54, "100GBASE_KR4"),
+ ice_arr_elem_idx(55, "100G_CAUI4_AOC_ACC"),
+ ice_arr_elem_idx(56, "100G_CAUI4"),
+ ice_arr_elem_idx(57, "100G_AUI4_AOC_ACC"),
+ ice_arr_elem_idx(58, "100G_AUI4"),
+ ice_arr_elem_idx(59, "100GBASE_CR_PAM4"),
+ ice_arr_elem_idx(60, "100GBASE_KR_PAM4"),
+ ice_arr_elem_idx(61, "100GBASE_CP2"),
+ ice_arr_elem_idx(62, "100GBASE_SR2"),
+ ice_arr_elem_idx(63, "100GBASE_DR"),
+};
+
+static const char * const ice_link_mode_str_high[] = {
+ ice_arr_elem_idx(0, "100GBASE_KR2_PAM4"),
+ ice_arr_elem_idx(1, "100G_CAUI2_AOC_ACC"),
+ ice_arr_elem_idx(2, "100G_CAUI2"),
+ ice_arr_elem_idx(3, "100G_AUI2_AOC_ACC"),
+ ice_arr_elem_idx(4, "100G_AUI2"),
+ ice_arr_elem_idx(5, "200G_CR4_PAM4"),
+ ice_arr_elem_idx(6, "200G_SR4"),
+ ice_arr_elem_idx(7, "200G_FR4"),
+ ice_arr_elem_idx(8, "200G_LR4"),
+ ice_arr_elem_idx(9, "200G_DR4"),
+ ice_arr_elem_idx(10, "200G_KR4_PAM4"),
+ ice_arr_elem_idx(11, "200G_AUI4_AOC_ACC"),
+ ice_arr_elem_idx(12, "200G_AUI4"),
+ ice_arr_elem_idx(13, "200G_AUI8_AOC_ACC"),
+ ice_arr_elem_idx(14, "200G_AUI8"),
+ ice_arr_elem_idx(15, "400GBASE_FR8"),
+};
+
/**
* dump_phy_type - helper function that prints PHY type strings
* @hw: pointer to the HW structure
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 42f2c33bd2..d680330369 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -84,6 +84,14 @@ ice_aq_get_internal_data(struct ice_hw *hw, u16 cluster_id, u16 table_id,
*/
#define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1))
+/* Define a macro for initializing array using indexes. Due to limitation
+ * of MSVC compiler it is necessary to allow other projects to replace
+ * that macro and strip the index from initialization.
+ * Linux driver is using coccinelle to maintain source sync with upstream
+ * and is not requiring this macro.
+ */
+#define ice_arr_elem_idx(idx, val) [(idx)] = (val)
+
int
ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
u32 rxq_index);
--
2.43.0