From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id EEA1B5F2F for ; Mon, 19 Mar 2018 10:08:41 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2018 02:08:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,329,1517904000"; d="scan'208";a="29205917" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga002.fm.intel.com with ESMTP; 19 Mar 2018 02:08:41 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 19 Mar 2018 02:08:40 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.226]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.129]) with mapi id 14.03.0319.002; Mon, 19 Mar 2018 17:08:37 +0800 From: "Xu, Rosen" To: "gaetan.rivet@6wind.com" CC: "dev@dpdk.org" , "Doherty, Declan" , "Richardson, Bruce" , "shreyansh.jain@nxp.com" , "Zhang, Tianfei" , "Wu, Hao" Thread-Topic: [RFC 0/5] Introduce Intel FPGA BUS Thread-Index: AQHTv2GfgYgiYhuj/E+xdOaXUjrfSaPXRNew Date: Mon, 19 Mar 2018 09:08:37 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D739F1FFDB@SHSMSX104.ccr.corp.intel.com> References: <1521097866-58282-1-git-send-email-rosen.xu@intel.com> <20180319090630.gvcffcx4cwet6zgm@bidouze.vm.6wind.com> In-Reply-To: <20180319090630.gvcffcx4cwet6zgm@bidouze.vm.6wind.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWJhMmI0YzgtYTg0MC00MDAyLTlkMGMtNGRiYTg2ZDM5N2JlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IlU4ZFZQanoxR3ZOb3BDWjZvQU9CTVwvRVB5aUp0SlRLNjlxQ0VuZWF4SkhJPSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [RFC 0/5] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Mar 2018 09:08:42 -0000 Got, many thanks for your reminder. -----Original Message----- From: Ga=EBtan Rivet [mailto:gaetan.rivet@6wind.com]=20 Sent: Monday, March 19, 2018 17:07 To: Xu, Rosen Cc: dev@dpdk.org; Doherty, Declan ; Richardson, B= ruce ; shreyansh.jain@nxp.com; Zhang, Tianfei <= tianfei.zhang@intel.com>; Wu, Hao Subject: Re: [RFC 0/5] Introduce Intel FPGA BUS Hi Rosen, On Thu, Mar 15, 2018 at 03:11:06PM +0800, Rosen Xu wrote: > Intel FPGA BUS in DPDK > ------------------------- >=20 > RFC [1]:=20 > http://www.dpdk.org/ml/archives/dev/2018-March/092297.html > http://www.dpdk.org/ml/archives/dev/2018-March/092298.html > http://www.dpdk.org/ml/archives/dev/2018-March/092299.html > http://www.dpdk.org/ml/archives/dev/2018-March/092300.html > http://www.dpdk.org/ml/archives/dev/2018-March/092301.html >=20 Have you had the time to read the section titled "Contribute by sending pat= ches" of the Development page from dpdk.org [1]? You need to generate the new thread with an increased version number (-v op= tion for git format-patch), generate the patchset using --thread, and send = the new version as a reply to the origin thread cover letter. These points are important for working over emails and allowing us to have = a clear view of your work. [1]: http://dpdk.org/dev Regards, -- Ga=EBtan Rivet 6WIND