From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 665137ECC for ; Wed, 9 May 2018 03:25:54 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 May 2018 18:25:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,379,1520924400"; d="scan'208";a="38464787" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga008.fm.intel.com with ESMTP; 08 May 2018 18:25:53 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 8 May 2018 18:25:52 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.240]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.6]) with mapi id 14.03.0319.002; Wed, 9 May 2018 09:25:50 +0800 From: "Xu, Rosen" To: Thomas Monjalon CC: "dev@dpdk.org" , "Doherty, Declan" , "Richardson, Bruce" , "shreyansh.jain@nxp.com" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Zhang, Tianfei" , "Liu, Song" , "Wu, Hao" , "gaetan.rivet@6wind.com" Thread-Topic: [PATCH v9 1/4] bus/ifpga: Add Intel FPGA BUS Library Thread-Index: AQHT5trY/M8Un1zLzEaGrSy4HFDM7qQmm2lQ Date: Wed, 9 May 2018 01:25:49 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D739FC6EA0@SHSMSX104.ccr.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1525789143-138168-1-git-send-email-rosen.xu@intel.com> <1525789143-138168-2-git-send-email-rosen.xu@intel.com> <3063017.5QX4IrYKZL@xps> In-Reply-To: <3063017.5QX4IrYKZL@xps> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjI3OWI5YjktNWI3ZC00YWIyLWJmYzQtZDU3N2NlZjA5NzAyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ2TkpuVGdQSERNMHQwd1htZGxBb0VcL0JlMUluUXh1YTNGRXk0VUdNeFB5ODhXN295MFZxOFwvdmFSNUVRc1RLNHUifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v9 1/4] bus/ifpga: Add Intel FPGA BUS Library X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 May 2018 01:25:54 -0000 Hi Thomas, > -----Original Message----- > From: Thomas Monjalon [mailto:thomas@monjalon.net] > Sent: Tuesday, May 08, 2018 22:43 > To: Xu, Rosen > Cc: dev@dpdk.org; Doherty, Declan ; > Richardson, Bruce ; shreyansh.jain@nxp.com; > Yigit, Ferruh ; Ananyev, Konstantin > ; Zhang, Tianfei ; > Liu, Song ; Wu, Hao ; > gaetan.rivet@6wind.com > Subject: Re: [PATCH v9 1/4] bus/ifpga: Add Intel FPGA BUS Library >=20 > 08/05/2018 16:19, Xu, Rosen: > > --- /dev/null > > +++ b/drivers/bus/ifpga/rte_bus_ifpga_version.map > > + ifpga_get_integer32_arg; > > + ifpga_get_string_arg; > > + rte_ifpga_driver_register; > > + rte_ifpga_driver_unregister; >=20 > All exported symbols must start with rte_ I will fix it in v10. >=20 > > --- a/drivers/bus/meson.build > > +++ b/drivers/bus/meson.build > > -drivers =3D ['dpaa', 'fslmc', 'pci', 'vdev'] > > +drivers =3D ['dpaa', 'fslmc', 'pci', 'vdev', 'ifpga'] >=20 > Would be better sorted in alphabetical order (between fslmc and pci). > Same comment in files config/common_base and drivers/bus/Makefile. I will fix in in v10.