From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id DA0941BA9F for ; Thu, 10 May 2018 14:20:50 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 May 2018 05:20:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,385,1520924400"; d="scan'208";a="227361044" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga005.fm.intel.com with ESMTP; 10 May 2018 05:20:49 -0700 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 10 May 2018 05:20:49 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 10 May 2018 05:20:49 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.240]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.40]) with mapi id 14.03.0319.002; Thu, 10 May 2018 20:20:46 +0800 From: "Xu, Rosen" To: "Wu, Jingjing" , "dev@dpdk.org" , "thomas@monjalon.net" CC: "Zhang, Roy Fan" , "Doherty, Declan" , "Richardson, Bruce" , "shreyansh.jain@nxp.com" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Zhang, Tianfei" , "Liu, Song" , "Wu, Hao" , "gaetan.rivet@6wind.com" Thread-Topic: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library Thread-Index: AQHT52lRfluNBgn+mkWPvGMkqxT8EqQolppggABMsYA= Date: Thu, 10 May 2018 12:20:46 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D739FD11D5@SHSMSX104.ccr.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1525851801-16101-1-git-send-email-rosen.xu@intel.com> <1525851801-16101-2-git-send-email-rosen.xu@intel.com> <9BB6961774997848B5B42BEC655768F81108EC6C@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <9BB6961774997848B5B42BEC655768F81108EC6C@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzliNmUwOTQtY2U0Mi00MDAzLWIxMGMtOWEzMzk2Njk2N2JjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJQVFNYbEVDMHE0aE0wMTdqdFNtYkRhUUNmWE5UVjlMZ1VhNVZ1NUU3Q2F5dDNJaFRnTERLbnlXZGR5UlJZZnVDIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 May 2018 12:20:51 -0000 Hi Jingjing, > -----Original Message----- > From: Wu, Jingjing > Sent: Thursday, May 10, 2018 16:44 > To: Xu, Rosen ; dev@dpdk.org; thomas@monjalon.net > Cc: Xu, Rosen ; Zhang, Roy Fan > ; Doherty, Declan ; > Richardson, Bruce ; shreyansh.jain@nxp.com; > Yigit, Ferruh ; Ananyev, Konstantin > ; Zhang, Tianfei ; > Liu, Song ; Wu, Hao ; > gaetan.rivet@6wind.com > Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS > Library >=20 > Hi, Rosen >=20 > Few comments below. Thanks a lot Jingjing. =20 >=20 > Thanks > Jingjing >=20 > [......] > > +static struct rte_ifpga_device * > > +ifpga_find_ifpga_dev(const struct rte_rawdev *rdev) { > > + struct rte_ifpga_device *ifpga_dev =3D NULL; > > + > > + TAILQ_FOREACH(ifpga_dev, &ifpga_device_list, next) { > > + if (rdev && > rdev -> ifpage_dev ?? Rdev doesn't has this variable. > > + ifpga_dev->rdev && > > + ifpga_dev->rdev =3D=3D rdev) > > + return ifpga_dev; > > + } > > + return NULL; > > +} > > + > > +static struct rte_afu_device * > > +ifpga_find_afu_dev(const struct rte_ifpga_device *ifpga_dev, > > + const struct rte_afu_id *afu_id) > > +{ > > + struct rte_afu_device *afu_dev =3D NULL; > > + > > + TAILQ_FOREACH(afu_dev, &ifpga_dev->afu_list, next) { > > + if (!ifpga_afu_id_cmp(&afu_dev->id, afu_id)) > Add checking afu_dev? Fixed. > [...] >=20 > > +static int > > +ifpga_parse(const char *name, void *addr) { > > + int *out =3D addr; > > + struct rte_rawdev *rawdev =3D NULL; > > + char rawdev_name[RTE_RAWDEV_NAME_MAX_LEN]; > > + char *c1 =3D NULL, *c2 =3D NULL; > According to coding style, we need to two lines for the definition like: > char *c1 =3D NULL; > char *c2 =3D NULL; Fixed > > + int port =3D IFPGA_BUS_DEV_PORT_MAX; > > + char str_port[8]; > > + int str_port_len =3D 0; > > + int ret; > > + > > + memset(str_port, 0, 8); > > + c1 =3D strchr(name, '|'); > > + if (c1 !=3D NULL) { > > + str_port_len =3D c1-name; > According to coding style, spaces are required around opreations. Fixed. > > + c2 =3D c1+1; > > + }