From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id DF9F11B1CB for ; Fri, 11 May 2018 15:45:41 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 May 2018 06:45:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,388,1520924400"; d="scan'208";a="41013242" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga006.jf.intel.com with ESMTP; 11 May 2018 06:45:40 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 11 May 2018 06:45:39 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 11 May 2018 06:45:39 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.240]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.40]) with mapi id 14.03.0319.002; Fri, 11 May 2018 21:45:36 +0800 From: "Xu, Rosen" To: "Zhang, Qi Z" , "dev@dpdk.org" , "thomas@monjalon.net" CC: "Zhang, Roy Fan" , "Doherty, Declan" , "Richardson, Bruce" , "shreyansh.jain@nxp.com" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Zhang, Tianfei" , "Liu, Song" , "Wu, Hao" , "gaetan.rivet@6wind.com" Thread-Topic: [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Thread-Index: AQHT6QKABw0lT9KsFkW79haUKImYpKQqb70ggAAa2JA= Date: Fri, 11 May 2018 13:45:36 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D739FD6E0E@SHSMSX104.ccr.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1526027491-30152-1-git-send-email-rosen.xu@intel.com> <039ED4275CED7440929022BC67E70611531B14C3@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <039ED4275CED7440929022BC67E70611531B14C3@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzlkNjFkZWMtYWQwMi00ODNlLTg1ZTUtZDI0OTYwYTU1MDY4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ6SkpJNUhjVExVMEVJZlB2SjkxUllDQU43T2hodTQ1SkJscWF2dW80RlVHXC8xTDQrOE5Mc2VMWUtKdmQwb0tTZCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 May 2018 13:45:42 -0000 Thanks Qi. > -----Original Message----- > From: Zhang, Qi Z > Sent: Friday, May 11, 2018 20:12 > To: Xu, Rosen ; dev@dpdk.org; > thomas@monjalon.net > Cc: Xu, Rosen ; Zhang, Roy Fan > ; Doherty, Declan ; > Richardson, Bruce ; shreyansh.jain@nxp.com; > Yigit, Ferruh ; Ananyev, Konstantin > ; Zhang, Tianfei ; > Liu, Song ; Wu, Hao ; > gaetan.rivet@6wind.com > Subject: RE: [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS >=20 >=20 >=20 > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Xu, Rosen > > Sent: Friday, May 11, 2018 4:31 PM > > To: dev@dpdk.org; thomas@monjalon.net > > Cc: Xu, Rosen ; Zhang, Roy Fan > > ; Doherty, Declan ; > > Richardson, Bruce ; > > shreyansh.jain@nxp.com; Yigit, Ferruh ; > > Ananyev, Konstantin ; Zhang, Tianfei > > ; Liu, Song ; Wu, Hao > > ; gaetan.rivet@6wind.com > > Subject: [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS > > > > From: "Xu, Rosen" > > > > Intel FPGA BUS in DPDK > > ------------------------- > > > > This patch set introduces Intel FPGA BUS support in DPDK. > > > Though opens remains, overall is OK, no objection for merge. >=20 > Reviewed-by: Qi Zhang >=20 >=20