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Thu, 23 May 2019 18:05:27 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.33]) by shsmsx102.ccr.corp.intel.com ([169.254.2.249]) with mapi id 14.03.0415.000; Fri, 24 May 2019 09:05:25 +0800 From: "Xu, Rosen" To: "Pei, Andy" , "dev@dpdk.org" CC: "Zhang, Roy Fan" , "Zhang, Qi Z" , "Wu, Jingjing" , "Xing, Beilei" , "Yigit, Ferruh" Thread-Topic: [PATCH] net/i40e: i40e rework for ipn3ke Thread-Index: AQHVEUjJ1L1jCoz7ekeOapBGuuSOYqZ5dm0A Date: Fri, 24 May 2019 01:05:25 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73A7781F5@SHSMSX104.ccr.corp.intel.com> References: <1558602875-429451-1-git-send-email-andy.pei@intel.com> In-Reply-To: <1558602875-429451-1-git-send-email-andy.pei@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiN2MyZDBlYjQtYjU1Yy00MWFlLTk1M2EtODdkYjZhZGFlODJhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZXpFTURSNDdONW55OWFQUmh2dVV1SjJtRmRwUzJpa05Eb3JUbnFKVVN6TzFSelR3eFFqcE9OcDdYczQrdzlhMyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: i40e rework for ipn3ke X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Pei, Andy > Sent: Thursday, May 23, 2019 17:15 > To: dev@dpdk.org > Cc: Pei, Andy ; Zhang, Roy Fan > ; Zhang, Qi Z ; Wu, > Jingjing ; Xing, Beilei ; Y= igit, > Ferruh ; Xu, Rosen > Subject: [PATCH] net/i40e: i40e rework for ipn3ke > Add switch_mode argument for i40e PF to specify the specific FPGA that i4= 0e > PF is connected to. > i40e PF get link status update via the connected FPGA. >=20 > Fixes: c60869e2b742 ("net/i40e: fix link status update") > Cc: roy.fan.zhang@intel.com > Cc: qi.z.zhang@intel.com > Cc: jingjing.wu@intel.com > Cc: beilei.xing@intel.com > Cc: ferruh.yigit@intel.com > Cc: rosen.xu@intel.com My understanding cc people should add in git send-email not in patch. > Signed-off-by: Andy Pei > --- > drivers/net/i40e/i40e_ethdev.c | 128 > +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 122 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethde= v.c > index cab440f..9873ea0 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -39,11 +39,12 @@ > #include "i40e_regs.h" > #include "rte_pmd_i40e.h" >=20 > -#define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" > -#define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" > -#define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" > -#define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" > -#define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" > +#define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" > +#define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" > +#define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" > +#define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" > +#define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" > +#define ETH_I40E_SWITCH_MODE_ARG "switch_mode" >=20 > #define I40E_CLEAR_PXE_WAIT_MS 200 >=20 > @@ -410,6 +411,7 @@ static int i40e_sw_tunnel_filter_insert(struct i40e_p= f > *pf, > ETH_I40E_SUPPORT_MULTI_DRIVER, > ETH_I40E_QUEUE_NUM_PER_VF_ARG, > ETH_I40E_USE_LATEST_VEC, > + ETH_I40E_SWITCH_MODE_ARG, > NULL}; >=20 > static const struct rte_pci_id pci_id_i40e_map[] =3D { @@ -2784,6 +2786,= 80 > @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) > } > } >=20 > +static int > +i40e_pf_parse_switch_mode(const char *key __rte_unused, > + const char *value, void *extra_args) > +{ > + if (!value || !extra_args) > + return -EINVAL; > + > + *(char **)extra_args =3D strdup(value); > + > + if (!*(char **)extra_args) > + return -ENOMEM; > + > + return 0; > +} > + > +static void > +i40e_pf_switch_mode_link_update(const char *cfg_str, > + struct rte_eth_dev **switch_ethdev) > +{ > + char switch_name[RTE_ETH_NAME_MAX_LEN] =3D {0}; > + char port_name[RTE_ETH_NAME_MAX_LEN] =3D {0}; > + char switch_ethdev_name[RTE_ETH_NAME_MAX_LEN] =3D {0}; > + uint16_t port_id; > + const char *p_src; > + char *p_dst; > + int ret =3D -1; > + > + /* An example of cfg_str is "IPN3KE_0@b3:00.0_0" */ > + if (!strncmp(cfg_str, "IPN3KE", strlen("IPN3KE"))) { > + p_src =3D cfg_str; > + PMD_DRV_LOG(DEBUG, "cfg_str is %s", cfg_str); > + > + /* move over "IPN3KE" */ > + while ((*p_src !=3D '_') && (*p_src)) > + p_src++; > + > + /* move over the first underline */ > + p_src++; > + > + p_dst =3D switch_name; > + while ((*p_src !=3D '_') && (*p_src)) { > + if (*p_src =3D=3D '@') { > + *p_dst++ =3D '|'; > + p_src++; > + } else > + *p_dst++ =3D *p_src++; > + } > + *p_dst =3D 0; > + PMD_DRV_LOG(DEBUG, "switch_name is %s", switch_name); > + > + /* move over the second underline */ > + p_src++; > + > + p_dst =3D port_name; > + while (*p_src) > + *p_dst++ =3D *p_src++; > + *p_dst =3D 0; > + PMD_DRV_LOG(DEBUG, "port_name is %s", port_name); > + > + snprintf(switch_ethdev_name, sizeof(switch_ethdev_name), > + "net_%s_representor_%s", switch_name, > port_name); > + PMD_DRV_LOG(DEBUG, "switch_ethdev_name is %s", > + switch_ethdev_name); > + > + ret =3D rte_eth_dev_get_port_by_name(switch_ethdev_name, > + &port_id); > + if (ret) > + *switch_ethdev =3D NULL; > + else > + *switch_ethdev =3D &rte_eth_devices[port_id]; > + } else > + *switch_ethdev =3D NULL; > +} > + > int > i40e_dev_link_update(struct rte_eth_dev *dev, > int wait_to_complete) > @@ -2792,6 +2868,11 @@ void i40e_flex_payload_reg_set_default(struct > i40e_hw *hw) > struct rte_eth_link link; > bool enable_lse =3D dev->data->dev_conf.intr_conf.lsc ? true : false; > int ret; > + struct rte_devargs *devargs; > + struct rte_kvargs *kvlist =3D NULL; > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > + struct rte_eth_dev *switch_ethdev; > + char *switch_cfg_str =3D NULL; >=20 > memset(&link, 0, sizeof(link)); >=20 > @@ -2805,6 +2886,40 @@ void i40e_flex_payload_reg_set_default(struct > i40e_hw *hw) > else > update_link_aq(hw, &link, enable_lse, wait_to_complete); >=20 > + devargs =3D pci_dev->device.devargs; > + if (devargs) { > + kvlist =3D rte_kvargs_parse(devargs->args, valid_keys); > + if (kvlist !=3D NULL) { > + if (rte_kvargs_count(kvlist, > ETH_I40E_SWITCH_MODE_ARG) > + =3D=3D 1) { > + if (!rte_kvargs_process(kvlist, > + ETH_I40E_SWITCH_MODE_ARG, > + &i40e_pf_parse_switch_mode, > + &switch_cfg_str)) { > + > + i40e_pf_switch_mode_link_update( > + switch_cfg_str, > + &switch_ethdev); > + > + if (switch_ethdev) { > + rte_eth_linkstatus_get( > + switch_ethdev, > + &link); > + } else { > + link.link_duplex =3D > + > ETH_LINK_FULL_DUPLEX; > + link.link_autoneg =3D > + > ETH_LINK_SPEED_FIXED; > + link.link_speed =3D > + > ETH_SPEED_NUM_25G; > + link.link_status =3D 0; > + } > + } > + } > + rte_kvargs_free(kvlist); > + } > + } > + > ret =3D rte_eth_linkstatus_set(dev, &link); > i40e_notify_all_vfs_link_status(dev); >=20 > @@ -12790,4 +12905,5 @@ struct i40e_customized_pctype* > ETH_I40E_FLOATING_VEB_LIST_ARG "=3D" > ETH_I40E_QUEUE_NUM_PER_VF_ARG > "=3D1|2|4|8|16" > ETH_I40E_SUPPORT_MULTI_DRIVER "=3D1" > - ETH_I40E_USE_LATEST_VEC "=3D0|1"); > + ETH_I40E_USE_LATEST_VEC "=3D0|1" > + ETH_I40E_SWITCH_MODE_ARG "=3DIPN3KE"); > -- > 1.8.3.1