From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FCCCA00BE; Thu, 31 Oct 2019 03:38:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 78B7D1C116; Thu, 31 Oct 2019 03:38:50 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id D8B49316B for ; Thu, 31 Oct 2019 03:38:48 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 19:38:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,249,1569308400"; d="scan'208";a="230687095" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga002.fm.intel.com with ESMTP; 30 Oct 2019 19:38:47 -0700 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 30 Oct 2019 19:38:46 -0700 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 30 Oct 2019 19:38:46 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Wed, 30 Oct 2019 19:38:46 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.127]) by shsmsx102.ccr.corp.intel.com ([169.254.2.108]) with mapi id 14.03.0439.000; Thu, 31 Oct 2019 10:38:44 +0800 From: "Xu, Rosen" To: "Ye, Xiaolong" , "Pei, Andy" CC: "dev@dpdk.org" , "Zhang, Tianfei" , "Yigit, Ferruh" Thread-Topic: [PATCH v14 00/19] add PCIe AER disable and IRQ support for ipn3ke Thread-Index: AQHVjW5H9+vKoVXVa0i3aEojJvNHvqdzfT+AgACQerA= Date: Thu, 31 Oct 2019 02:38:44 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73AB08BD6@SHSMSX104.ccr.corp.intel.com> References: <1571917119-149534-2-git-send-email-andy.pei@intel.com> <1572252623-96127-1-git-send-email-andy.pei@intel.com> <20191031020129.GJ11315@intel.com> In-Reply-To: <20191031020129.GJ11315@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODdkZGJiYWYtZDQxYi00OWI5LTgwOGEtMmExYzFkZmEwYWFjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUTlNaFNBOUxvR3JpeVQzTHVRNDYwQWREcVNjdCtJYkVTcW1RVStVQUhacDJNWjRwejlKTERwUTltY0NxZkphcyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v14 00/19] add PCIe AER disable and IRQ support for ipn3ke X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Thanks Xiaolong. > -----Original Message----- > From: Ye, Xiaolong > Sent: Thursday, October 31, 2019 10:01 > To: Pei, Andy > Cc: dev@dpdk.org; Xu, Rosen ; Zhang, Tianfei > ; Yigit, Ferruh > Subject: Re: [PATCH v14 00/19] add PCIe AER disable and IRQ support for > ipn3ke >=20 > On 10/28, Andy Pei wrote: > >This patch set adds PCIe AER disable and FPGA interrupt support for > >ipn3ke. It also provides a small rework for port bonding between FPGA > >line side port and I40e PF port. > > > >What is the PCI Express AER(Advanced Error Reporting)? > >Advanced Error Reporting capability is implemented with a PCI Express > >advanced error reporting extended capability structure providing more > >robust error reporting. It's also one of PCI Express error reporting > >paradigms. AER is supported by most of PCIe devices. > > > >In PAC N3000 card, some uncertainty errors will cause FPGA reload, such > >as temperature is higher than threshold. From Software point of view, > >FPGA reload means FPGA unplug and plug. For avoiding system crash we > >need to clear AER register before these errors occur. > > > >Currently PAC N3000 card FME and AFU all provide interrupts, in ifpga > >rawdev driver, we implement a FME interrupt function to notify errors > >reported by FME. Besides this, OPAE share code also provide a common > >AFU interrupt API for users to register their own interrupt functions. > > >=20 > Series applied to dpdk-next-net-intel. Thanks.