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From: "Xu, Rosen" <rosen.xu@intel.com>
To: "Chautru, Nicolas" <nicolas.chautru@intel.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: "Richardson, Bruce" <bruce.richardson@intel.com>,
	"O'Hare, Cathal" <cathal.ohare@intel.com>,
	"akhil.goyal@nxp.com" <akhil.goyal@nxp.com>,
	"Yigit, Ferruh" <ferruh.yigit@intel.com>,
	"O'Driscoll, Tim" <tim.odriscoll@intel.com>,
	"Mcnamara, John" <john.mcnamara@intel.com>
Subject: Re: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add queue	configuration
Date: Thu, 16 Apr 2020 01:09:17 +0000	[thread overview]
Message-ID: <0E78D399C70DA940A335608C6ED296D73AF191EA@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <1183128033837D43A851F70F33ED5C57893C3323@ORSMSX155.amr.corp.intel.com>

Hi,

> -----Original Message-----
> From: Chautru, Nicolas <nicolas.chautru@intel.com>
> Sent: Wednesday, April 15, 2020 23:51
> To: Xu, Rosen <rosen.xu@intel.com>; dev@dpdk.org
> Cc: Richardson, Bruce <bruce.richardson@intel.com>; O'Hare, Cathal
> <cathal.ohare@intel.com>; akhil.goyal@nxp.com
> Subject: RE: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add
> queue configuration
> 
> Hi
> 
> > From: Xu, Rosen <rosen.xu@intel.com>
> > Hi,
> >
> > > -----Original Message-----
> > > From: Chautru, Nicolas <nicolas.chautru@intel.com>
> > > Sent: Tuesday, April 14, 2020 8:16
> > > To: Xu, Rosen <rosen.xu@intel.com>; dev@dpdk.org;
> > > akhil.goyal@nxp.com
> > > Cc: Richardson, Bruce <bruce.richardson@intel.com>
> > > Subject: RE: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add
> > > queue configuration
> > >
> > > Thanks Rosen for your thorough code review. Some comments in-line
> below.
> > >
> > > > From: Xu, Rosen <rosen.xu@intel.com>
> > > >
> > > > Hi,
> > > >
> > > > Could you prefix all functions name with the FPGA IP name? FPGA is
> > > > a very common device name.
> > > >
> > >
> > > I don't see such a guideline being used across all other PMDs.
> > > Unsure it always help notably as this would create many long
> > > function names with fpga_5gnr_fec_ added each time, and these names
> > > are not exposed outside of this .c file.
> > > Also some of the fpga_ prefixes would apply for either fpga_lte_fec
> > > or fpga_5gnr_fec PMD.
> > > If this becomes of a new guide lines we can rename every single
> > > function in each existing baseband PMD in future release (not just
> > > this new
> > PMD).
> >
> > What I mentioned is that, let's take FVL for example, in our PMD, we
> > name it's PMD functions with I40e_xxx, i40e is Intel NIC name, but for
> > your design it named with fpga_5gnr_xxx, fpga is a common device, That
> > means not Intel only provide FPGA, no sure if any other developer
> > summit other FPGA based 5G acceleration IP, is it ok?
> >
> 
> The new baseband PMD is indeed called "fpga_5gnr_fec" which may sound
> fairly generic.
> Note that that an older existing baseband PMD is currently called
> "fpga_lte_fec", the new PMD is the 5G version while the previous provided
> 4G capability. This depends on the user image being loaded onto the FPGA
> chip.
> Both these PMDs are in effect currently used by the ecosystem with the
> FPGA variant from Intel called Vista Creek (based on Altera Arria10 chip) but
> there is no limitation for same driver to be used on other chip (notably with
> increased cell density on newer process) as long as the HW ring interface is
> the same or compatible image is loaded agnostically on the chip.
> 
> Let me know if unclear.
> 
> 
> 
It's better to name your PMD and functions as IP name prefix not FPGA name, FPGA is a very common device.

Reviewed-by: Rosen Xu <rosen.xu@intel.com>

  reply	other threads:[~2020-04-16  1:09 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-30  0:02 [dpdk-dev] [PATCH v2 00/13] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 01/13] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 02/13] bbdev: expose device HARQ buffer size at device level Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 03/13] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 04/13] baseband/fpga_5gnr_fec: add register definition file Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 05/13] baseband/fpga_5gnr_fec: add device info_get function Nicolas Chautru
2020-04-16 18:15   ` Akhil Goyal
2020-04-16 21:20     ` Chautru, Nicolas
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add queue configuration Nicolas Chautru
2020-04-11  3:13   ` Xu, Rosen
2020-04-14  0:16     ` Chautru, Nicolas
2020-04-15  6:13       ` Xu, Rosen
2020-04-15 15:51         ` Chautru, Nicolas
2020-04-16  1:09           ` Xu, Rosen [this message]
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 07/13] baseband/fpga_5gnr_fec: add LDPC processing functions Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 08/13] baseband/fpga_5gnr_fec: add HW error capture Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 09/13] baseband/fpga_5gnr_fec: add debug functionality Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 10/13] baseband/fpga_5gnr_fec: add configure function Nicolas Chautru
2020-04-15 15:40   ` Power, Niall
2020-04-16 19:30   ` Akhil Goyal
2020-04-16 21:45     ` Chautru, Nicolas
2020-05-01 23:15       ` Chautru, Nicolas
2020-05-04 17:19         ` Thomas Monjalon
2020-06-25  0:30           ` Chautru, Nicolas
2020-06-25  8:13             ` Thomas Monjalon
2020-06-26  1:14               ` Chautru, Nicolas
2020-06-26 10:08                 ` Thomas Monjalon
2020-07-10 22:48                   ` Chautru, Nicolas
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 11/13] baseband/fpga_5gnr_fec: add harq loopback capability Nicolas Chautru
2020-03-30  0:02 ` [dpdk-dev] [PATCH v2 12/13] baseband/fpga_5gnr_fec: add interrupt support Nicolas Chautru
2020-04-16 18:43   ` Akhil Goyal
2020-03-30  0:03 ` [dpdk-dev] [PATCH v2 13/13] doc: add feature matrix table for bbdev devices Nicolas Chautru
2020-04-15 15:40 ` [dpdk-dev] [PATCH v2 00/13] drivers/baseband: add PMD for FPGA 5GNR FEC Power, Niall

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