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Wed, 9 Jan 2019 10:22:40 +0000 From: Yongseok Koh To: Jerin Jacob Kollanukkaran CC: Thomas Monjalon , Shahaf Shuler , "Gavin.Hu@arm.com" , "bluca@debian.org" , "dev@dpdk.org" Thread-Topic: [EXT] [PATCH] config: change default cache line size for ARMv8 with meson Thread-Index: AQHUqANwYgSIDCOae0ardNgcuhiCBaWmuneA Date: Wed, 9 Jan 2019 10:22:40 +0000 Message-ID: <0F6E5E54-EC4A-42AD-AF67-D901802F24E3@mellanox.com> References: <20190109093915.40882-1-yskoh@mellanox.com> <68eb1e77e09e396a229920f10487b6e95ddce5c8.camel@marvell.com> In-Reply-To: <68eb1e77e09e396a229920f10487b6e95ddce5c8.camel@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB3PR0502MB3962; 6:hBzZBEWGPBbsi0gpmFUKA73NqOE47JgO0wROlXyeTUXJj38VfUGM4Xdfik1BMj+GZeIhhfK5I3Y8UxCYJ9FRIfa5FnxGafLQF7j4FAjhFPE+Tpxy6CHZiJ+gOqj0p0JAd02PrNyUrmfNh5bozXQoXeCP1cwcJFq2B0S8l1O8uC2sn9WqIzxlXtPzhzLtmIqzQ5VsWMXRhvKCCq0q57W8HbazhKTOW3lPlXBccYVMtzH7OVY2uUfznnYAA4z/tPn3T4+izGbhyXOMWfiTW5JOxiRxIiNjoHeyyUVfqJWfiHMMcksH6mYSKqFHvTr45PZLsFFgn/x0TOLHmoFa8GH+dXZ5V+3ae6IkNCm862SMmn6WScdfWVrtEF6aqTkFMhXLYGSnoRUQsTcT8yup7CfeGFRAMnoErPy5KYn5kJyIT7ptw1ma0MfzUE2jX8Lbik5mV6G2swdlEh03AeaCj0HS1w==; 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charset="us-ascii" Content-ID: <5A904D19268EC94B8BAD1FE1C4CAB6D0@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: fffe8984-6a85-4608-7870-08d6761c62d0 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2019 10:22:40.7324 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3962 Subject: Re: [dpdk-dev] [EXT] [PATCH] config: change default cache line size for ARMv8 with meson X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Jan 2019 10:22:44 -0000 > On Jan 9, 2019, at 2:09 AM, Jerin Jacob Kollanukkaran wrote: >=20 > On Wed, 2019-01-09 at 01:39 -0800, Yongseok Koh wrote: >>=20 >> ------------------------------------------------------------------- >> --- >> In config/arm64_armv8_linuxapp_gcc, maximum available cache line size >> (128B) in arm64 implementations is set by default for generic config. >> However, setting 64B is preferable for meson build in order to >> support >> majority of CPUs which don't have Implementor ID or Part Number >> programmed >> on chip. >=20 > Adding Luca to get input from distro build perspective. >=20 > If I understand it correctly, distro build will be using > the generic config/arm/arm64_armv8_linuxapp_gcc for generic build. > If so, We can not change cache line size for generic config > as mentined the reason are > https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fmail= s.dpdk.org%2Farchives%2Fdev%2F2019-January%2F122441.html&data=3D02%7C01= %7Cyskoh%40mellanox.com%7Cf0818214ecbf492d5c1408d6761a9136%7Ca652971c7d2e4d= 9ba6a4d149256f461b%7C0%7C0%7C636826253828868015&sdata=3D7pT%2BPTNslOpTC= IqFjaZ223Hg3btpDB3dGC9xiy13wDA%3D&reserved=3D0 My understanding from your comment was distro build doesn't use meson but make with config/defconfig_arm64-armv8a-linuxapp-gcc. Let's hear from Luca. > I think, I way forward is to add config/arm/arm64_a72_linuxapp_gcc > for meson. This config can be used for all SoC with A72 armv8=20 > implementation and may have sym link to specfific SoC to avoid > confusion to end users. Is config/arm/arm64_a72_linuxapp_gcc valid? Others have arm64_[IMPLEMENTOR]= _linuxapp_gcc. a72 is got from PartNum. Thanks, Yongseok >>=20 >> Signed-off-by: Yongseok Koh >> --- >>=20 >> Discussion on the mailing list: >> https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2F= mails.dpdk.org%2Farchives%2Fdev%2F2019-January%2F122441.html&data=3D02%= 7C01%7Cyskoh%40mellanox.com%7Cf0818214ecbf492d5c1408d6761a9136%7Ca652971c7d= 2e4d9ba6a4d149256f461b%7C0%7C0%7C636826253828868015&sdata=3D7pT%2BPTNsl= OpTCIqFjaZ223Hg3btpDB3dGC9xiy13wDA%3D&reserved=3D0 >>=20 >> config/arm/meson.build | 11 +++++++---- >> 1 file changed, 7 insertions(+), 4 deletions(-) >>=20 >> diff --git a/config/arm/meson.build b/config/arm/meson.build >> index dae55d6b26..3af256a5ec 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -47,8 +47,7 @@ flags_common_default =3D [ >> flags_generic =3D [ >> ['RTE_MACHINE', '"armv8a"'], >> ['RTE_MAX_LCORE', 256], >> - ['RTE_USE_C11_MEM_MODEL', true], >> - ['RTE_CACHE_LINE_SIZE', 128]] >> + ['RTE_USE_C11_MEM_MODEL', true]] >> flags_cavium =3D [ >> ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> @@ -89,15 +88,19 @@ impl_dpaa2 =3D ['NXP DPAA2', flags_dpaa2, >> machine_args_generic] >>=20 >> dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) >>=20 >> +# In config/arm64_armv8_linuxapp_gcc, maximum available cache line >> size (128B) >> +# in arm64 implementations is set by default for generic config. >> However, >> +# setting 64B is preferable for meson build in order to support >> majority of CPUs >> +# which don't have Implementor ID or Part Number programmed on chip. >> +dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) >> + >> if cc.sizeof('void *') !=3D 8 >> - dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) >> dpdk_conf.set('RTE_ARCH_ARM', 1) >> dpdk_conf.set('RTE_ARCH_ARMv7', 1) >> # the minimum architecture supported, armv7-a, needs the >> following, >> # mk/machine/armv7a/rte.vars.mk sets it too >> machine_args +=3D '-mfpu=3Dneon' >> else >> - dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128) >> dpdk_conf.set('RTE_ARCH_ARM64', 1) >> dpdk_conf.set('RTE_ARCH_64', 1) >>=20