From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60C7D41F50; Wed, 12 Jun 2024 17:20:26 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B572742F99; Wed, 12 Jun 2024 17:06:15 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 8149442F7B for ; Wed, 12 Jun 2024 17:06:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204773; x=1749740773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jaM3ScQ2IMd+XPzEJ8uA9Gy94GnDY+9OI1T4C1/PMYc=; b=minjEOCXxO0gFE2w0TJxgv5szYu6NDZ8RhhI4pXcM4hs5054WrXoS9w7 6uKKBL1FKXiYRznVu50z4UbN3Y4D9WE8h7Sf73h4qfyx7g8MHEL8lVGfd 5GF1uwiaqEo1DbyrH4a0cN3LpC9WBoGfWYOdr6aMhLJG2tSHequg2BxcC IZnfeFkNRRIYkhoOogwfHs7rpb3GbLOqPHyQHH4NNfkdF2Xru6+TyJ9f7 cMVXclC/FNQ4hkTz/ADDtzErC9OLGK9BKVHK24sNi2TDVSxwzuisNQgNZ wq9PQzC0LpUb9xwaYaqAhBs6hfw+FtyM0mtpoMOT0AdGfB4b4wZT6lnmC A==; X-CSE-ConnectionGUID: iVH8NHNkS9mQXE18sNQr6A== X-CSE-MsgGUID: ZRszA9M1QUC8VvxqxyaqXg== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459891" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459891" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:06:12 -0700 X-CSE-ConnectionGUID: C7j2sKniRDGPFCoiKD6EUQ== X-CSE-MsgGUID: joZZBzVSSx6bdtRhhv5uuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925836" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:06:11 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Grzegorz Nitka Subject: [PATCH v2 106/148] net/ice/base: fix iterations over PTP ports Date: Wed, 12 Jun 2024 16:01:40 +0100 Message-ID: <0a59c58a3c40df273dfd0caee562a026f8cac541.1718204529.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes Replace 'phy_ports' with 'max_phy_port' for max range in iterations over PTP ports in case of ETH56G based devices. Signed-off-by: Grzegorz Nitka Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 1928d92b67..72a11a7e39 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1041,7 +1041,7 @@ ice_write_phy_port_eth56g_lp(struct ice_hw *hw, u8 port, u32 reg_offs, u32 val, int err; u32 reg_addr; - if (port >= hw->phy_ports) + if (port >= hw->max_phy_port) return ICE_ERR_OUT_OF_RANGE; err = ice_phy_port_res_address_eth56g(phy_port, res_type, reg_offs, @@ -1072,7 +1072,7 @@ ice_read_phy_port_eth56g_lp(struct ice_hw *hw, u8 port, u32 reg_offs, u32 *val, int err; u32 reg_addr; - if (port >= hw->phy_ports) + if (port >= hw->max_phy_port) return ICE_ERR_OUT_OF_RANGE; err = ice_phy_port_res_address_eth56g(phy_port, res_type, reg_offs, @@ -1489,7 +1489,7 @@ static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) { unsigned int port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; @@ -1547,7 +1547,7 @@ ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) */ phy_time = (u64)time << 32; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { int err; if (!(hw->ena_lports & BIT(port))) continue; @@ -1644,7 +1644,7 @@ ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq) */ cycles = (s64)adj << 32; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; @@ -1670,7 +1670,7 @@ ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) { u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { int err; if (!(hw->ena_lports & BIT(port))) continue; @@ -1732,7 +1732,7 @@ ice_ptp_prep_phy_adj_target_eth56g(struct ice_hw *hw, u32 target_time) int err; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; @@ -1919,7 +1919,7 @@ ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, int err; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; @@ -2043,7 +2043,7 @@ static int ice_ptp_clear_phy_offset_ready_eth56g(struct ice_hw *hw) { u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { int err; err = ice_write_phy_reg_eth56g(hw, port, @@ -3058,7 +3058,7 @@ int ice_ptp_set_vernier_wl(struct ice_hw *hw) { u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { int err; err = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL, @@ -3123,7 +3123,7 @@ ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time) */ phy_time = (u64)time << 32; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { /* Tx case */ err = ice_write_64b_phy_reg_e822(hw, port, @@ -3232,7 +3232,7 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq) else cycles = -(((s64)-adj) << 32); - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { int err; err = ice_ptp_prep_port_adj_e822(hw, port, cycles, lock_sbq); @@ -3258,7 +3258,7 @@ ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval) int err; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval); if (err) @@ -3319,7 +3319,7 @@ ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32 target_time) int err; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { /* Tx case */ /* No sub-nanoseconds data */ @@ -4254,7 +4254,7 @@ static int ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw) { u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { int err; err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); -- 2.43.0