From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F0719A04B6; Mon, 12 Oct 2020 21:32:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9FEF81C1D8; Mon, 12 Oct 2020 21:32:06 +0200 (CEST) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by dpdk.org (Postfix) with ESMTP id 7C1051C19B for ; Mon, 12 Oct 2020 21:32:04 +0200 (CEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09CJGK9s116437; Mon, 12 Oct 2020 15:32:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=MYIIPhjKBJFeLkI6iaSIiLNgcKC96+UR9Gq4EhgDXMI=; b=S0SH0VyDI9wnPudY9FrfBgyY3NMuJXn+rP8OWMW1mi8uq0i7EOGNcRTpMncb7lX2lC+j Ip3jQQIhsqLa3H7StKdwblwfREUREODd67KILDeN4TaKI9yGwEq14I7ByE430jEF+TC4 ao8NiXPhzVulf7VQjNwIi8rL+mg5G/IJCQJBIsSf8BAplw8fncgFu4NbgCZWT02VQ1ns s9pU930KnV5ux3eOaTmhnJNekGNHNIh+/KEUJfvVJbX1VriL+wh6pO4fi6TKBgztT6FU 7PXK/trt2QsKIMnBK+jHBt5vISlQpQfuNopqLHJLrcQWTaNidaxoIW93sRxIKSpUKW9o zw== Received: from ppma01dal.us.ibm.com (83.d6.3fa9.ip4.static.sl-reverse.com [169.63.214.131]) by mx0b-001b2d01.pphosted.com with ESMTP id 344w5g0992-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 12 Oct 2020 15:32:02 -0400 Received: from pps.filterd (ppma01dal.us.ibm.com [127.0.0.1]) by ppma01dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 09CJVp6E003040; Mon, 12 Oct 2020 19:32:01 GMT Received: from b03cxnp08025.gho.boulder.ibm.com (b03cxnp08025.gho.boulder.ibm.com [9.17.130.17]) by ppma01dal.us.ibm.com with ESMTP id 3434k8xggu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 12 Oct 2020 19:32:01 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 09CJVtlB58065232 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 12 Oct 2020 19:31:55 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DA0CE6A047; Mon, 12 Oct 2020 19:31:59 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 72F806A051; Mon, 12 Oct 2020 19:31:59 +0000 (GMT) Received: from Davids-MBP.randomparity.org (unknown [9.211.73.22]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 12 Oct 2020 19:31:59 +0000 (GMT) To: Omkar Maslekar , dev@dpdk.org Cc: bruce.richardson@intel.com, ciara.loftus@intel.com, jerinj@marvell.com, ruifeng.wang@arm.com, honnappa.nagarahalli@arm.com References: <1599700614-22809-1-git-send-email-omkar.maslekar@intel.com> <1602497980-20680-1-git-send-email-omkar.maslekar@intel.com> <1602497980-20680-2-git-send-email-omkar.maslekar@intel.com> From: David Christensen Message-ID: <0f6c65bd-901b-cc0f-1510-0fd08227f8c4@linux.vnet.ibm.com> Date: Mon, 12 Oct 2020 12:31:59 -0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: <1602497980-20680-2-git-send-email-omkar.maslekar@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-10-12_15:2020-10-12, 2020-10-12 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 clxscore=1015 bulkscore=0 mlxscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010120139 Subject: Re: [dpdk-dev] [PATCH v6] eal: add cache-line demote support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 10/12/20 3:19 AM, Omkar Maslekar wrote: > rte_cldemote is similar to a prefetch hint - in reverse. cldemote(addr) > enables software to hint to hardware that line is likely to be shared. > Useful in core-to-core communications where cache-line is likely to be > shared. ARM and PPC implementation is provided with NOP and can be added > if any equivalent instructions could be used for implementation on those > architectures. > > Signed-off-by: Omkar Maslekar > Acked-by: Bruce Richardson > > --- > v6: marked rte_cldemote as experimental > added rte_cldemote call in existing app/test_prefetch.c > > v5: documentation updated > fixed formatting issue in release notes > added Acked-by: Bruce Richardson > * > v4: updated bold text for title and fixed margin in release notes > * > v3: fixed warning regarding whitespace > * > v2: documentation updated > --- > --- > app/test/test_prefetch.c | 4 ++++ > doc/guides/rel_notes/release_20_11.rst | 7 +++++++ > lib/librte_eal/arm/include/rte_prefetch_32.h | 8 ++++++++ > lib/librte_eal/arm/include/rte_prefetch_64.h | 8 ++++++++ > lib/librte_eal/include/generic/rte_prefetch.h | 16 ++++++++++++++++ > lib/librte_eal/ppc/include/rte_prefetch.h | 8 ++++++++ > lib/librte_eal/x86/include/rte_prefetch.h | 12 ++++++++++++ > 7 files changed, 63 insertions(+) ...snip... > diff --git a/lib/librte_eal/ppc/include/rte_prefetch.h b/lib/librte_eal/ppc/include/rte_prefetch.h > index 9ba07c8..9630227 100644 > --- a/lib/librte_eal/ppc/include/rte_prefetch.h > +++ b/lib/librte_eal/ppc/include/rte_prefetch.h > @@ -11,6 +11,7 @@ > #endif > > #include > +#include > #include "generic/rte_prefetch.h" > > static inline void rte_prefetch0(const volatile void *p) > @@ -34,6 +35,13 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) > rte_prefetch0(p); > } > > +static inline void > +__rte_experimental > +rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} > + > #ifdef __cplusplus > } > #endif Don't see an equivalent operation in the 3.1 ISA for POWER processors, so NOP is the right implementation. Acked-by: David Christensen