From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id E62D24C95 for ; Fri, 15 Mar 2019 18:54:17 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Mar 2019 10:54:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,482,1544515200"; d="scan'208";a="307589391" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.46]) ([10.237.221.46]) by orsmga005.jf.intel.com with ESMTP; 15 Mar 2019 10:54:15 -0700 To: Wenzhuo Lu , dev@dpdk.org References: <1551340136-83843-1-git-send-email-wenzhuo.lu@intel.com> <1552630975-62900-1-git-send-email-wenzhuo.lu@intel.com> <1552630975-62900-7-git-send-email-wenzhuo.lu@intel.com> From: Ferruh Yigit Openpgp: preference=signencrypt Autocrypt: addr=ferruh.yigit@intel.com; prefer-encrypt=mutual; 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WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.3 MIME-Version: 1.0 In-Reply-To: <1552630975-62900-7-git-send-email-wenzhuo.lu@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v3 6/8] net/ice: support Rx AVX2 vector X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Mar 2019 17:54:18 -0000 On 3/15/2019 6:22 AM, Wenzhuo Lu wrote: > Signed-off-by: Wenzhuo Lu <...> > +#ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC > + /* for AVX we need alignment otherwise loads are not atomic */ > + if (avx_aligned) { > + /* load in descriptors, 2 at a time, in reverse order */ > + raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6)); > + rte_compiler_barrier(); > + raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4)); > + rte_compiler_barrier(); > + raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2)); > + rte_compiler_barrier(); > + raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0)); > + } else > +#endif > + do { > + const __m128i raw_desc7 = > + _mm_load_si128((void *)(rxdp + 7)); > + rte_compiler_barrier(); > + const __m128i raw_desc6 = > + _mm_load_si128((void *)(rxdp + 6)); > + rte_compiler_barrier(); > + const __m128i raw_desc5 = > + _mm_load_si128((void *)(rxdp + 5)); > + rte_compiler_barrier(); > + const __m128i raw_desc4 = > + _mm_load_si128((void *)(rxdp + 4)); > + rte_compiler_barrier(); > + const __m128i raw_desc3 = > + _mm_load_si128((void *)(rxdp + 3)); > + rte_compiler_barrier(); > + const __m128i raw_desc2 = > + _mm_load_si128((void *)(rxdp + 2)); > + rte_compiler_barrier(); > + const __m128i raw_desc1 = > + _mm_load_si128((void *)(rxdp + 1)); > + rte_compiler_barrier(); > + const __m128i raw_desc0 = > + _mm_load_si128((void *)(rxdp + 0)); > + > + raw_desc6_7 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc6), > + raw_desc7, 1); > + raw_desc4_5 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc4), > + raw_desc5, 1); > + raw_desc2_3 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc2), > + raw_desc3, 1); > + raw_desc0_1 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc0), > + raw_desc1, 1); > + } while (0); Is this to provide the proper indention because of the above #ifdef block? If so why not simple { } for the scope, is do{ }while(0) has benefit against it? From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 35DECA0096 for ; Fri, 15 Mar 2019 18:54:20 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0BDE34C96; Fri, 15 Mar 2019 18:54:20 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id E62D24C95 for ; Fri, 15 Mar 2019 18:54:17 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Mar 2019 10:54:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,482,1544515200"; d="scan'208";a="307589391" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.46]) ([10.237.221.46]) by orsmga005.jf.intel.com with ESMTP; 15 Mar 2019 10:54:15 -0700 To: Wenzhuo Lu , dev@dpdk.org References: <1551340136-83843-1-git-send-email-wenzhuo.lu@intel.com> <1552630975-62900-1-git-send-email-wenzhuo.lu@intel.com> <1552630975-62900-7-git-send-email-wenzhuo.lu@intel.com> From: Ferruh Yigit Openpgp: preference=signencrypt Autocrypt: addr=ferruh.yigit@intel.com; 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WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.3 MIME-Version: 1.0 In-Reply-To: <1552630975-62900-7-git-send-email-wenzhuo.lu@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v3 6/8] net/ice: support Rx AVX2 vector X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190315175415.9wAqEcaR5E1j2HjxMjYUo87KgJLQolV19or8Z1y1Hy8@z> On 3/15/2019 6:22 AM, Wenzhuo Lu wrote: > Signed-off-by: Wenzhuo Lu <...> > +#ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC > + /* for AVX we need alignment otherwise loads are not atomic */ > + if (avx_aligned) { > + /* load in descriptors, 2 at a time, in reverse order */ > + raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6)); > + rte_compiler_barrier(); > + raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4)); > + rte_compiler_barrier(); > + raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2)); > + rte_compiler_barrier(); > + raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0)); > + } else > +#endif > + do { > + const __m128i raw_desc7 = > + _mm_load_si128((void *)(rxdp + 7)); > + rte_compiler_barrier(); > + const __m128i raw_desc6 = > + _mm_load_si128((void *)(rxdp + 6)); > + rte_compiler_barrier(); > + const __m128i raw_desc5 = > + _mm_load_si128((void *)(rxdp + 5)); > + rte_compiler_barrier(); > + const __m128i raw_desc4 = > + _mm_load_si128((void *)(rxdp + 4)); > + rte_compiler_barrier(); > + const __m128i raw_desc3 = > + _mm_load_si128((void *)(rxdp + 3)); > + rte_compiler_barrier(); > + const __m128i raw_desc2 = > + _mm_load_si128((void *)(rxdp + 2)); > + rte_compiler_barrier(); > + const __m128i raw_desc1 = > + _mm_load_si128((void *)(rxdp + 1)); > + rte_compiler_barrier(); > + const __m128i raw_desc0 = > + _mm_load_si128((void *)(rxdp + 0)); > + > + raw_desc6_7 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc6), > + raw_desc7, 1); > + raw_desc4_5 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc4), > + raw_desc5, 1); > + raw_desc2_3 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc2), > + raw_desc3, 1); > + raw_desc0_1 = > + _mm256_inserti128_si256 > + (_mm256_castsi128_si256(raw_desc0), > + raw_desc1, 1); > + } while (0); Is this to provide the proper indention because of the above #ifdef block? If so why not simple { } for the scope, is do{ }while(0) has benefit against it?