From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30D2645501; Wed, 26 Jun 2024 14:07:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 05A0B434C4; Wed, 26 Jun 2024 13:57:34 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 0114242E95 for ; Wed, 26 Jun 2024 13:45:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402353; x=1750938353; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cC4kOYavMp2jJizUo6uD1XU4R2M1ijAKtixCOb8rfJ4=; b=PWN3RLmMHoRAz/lt5C4okYmcX6b3ImGsGIg1KefjPTZzw27WKh+ld42p ADOl9lrI5obrqZ0aGVak+zqwPv5WUbaQQSLrKC/JybHs78c2AjSIXINYx kF+FHAskDDiDe9Afksj6xqoomMBIp//pqryKf85jfaEmlg+8l8z7ogP4x nFgs2QCJ0L052DpNy+yBLU8gkAo7a1DsQLAbJYJyxQiUE06/sB/0jz2BM yfwXExxd+z1r75wppVa14QwZ/VGKUZNIVwDnISwPwXPV+NoqwYhrkBpxv uugDkNXvE15xZPR0C+0D5W8hd390ZbAppbqaUv/qeWa9sYCHbxNLP7/Lb w==; X-CSE-ConnectionGUID: +k+PUybzSjeLiF6J/97+9Q== X-CSE-MsgGUID: K4Y9sKPuQNmXLieV5LV1pw== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979635" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979635" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:45:52 -0700 X-CSE-ConnectionGUID: HNDPCSNFQeyCRsnSeNTIwQ== X-CSE-MsgGUID: FeIWMeAYQiO85KDL/fxniw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874859" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:45:52 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 100/103] net/ice/base: make some functions static Date: Wed, 26 Jun 2024 12:42:28 +0100 Message-ID: <1047aec35821abfe1e96acd3233f001849a39cd9.1719401848.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org To better align with upstream release, remove some functions from switch header and make them static instead. Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 14 +++++++------- drivers/net/ice/base/ice_ptp_hw.h | 16 ---------------- 2 files changed, 7 insertions(+), 23 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index b3b58f76d6..004f659eae 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3412,7 +3412,7 @@ ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts, * Note there is no equivalent of this operation on E810, as that device * always handles all external PHYs internally. */ -int +static int ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) { @@ -5072,8 +5072,8 @@ ice_ptp_prep_phy_adj_target_e810(struct ice_hw *hw, u32 target_time) * Prepare the external PHYs connected to this device for a timer sync * command. */ -int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, - bool lock_sbq) +static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, + bool lock_sbq) { u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); int err; @@ -5516,7 +5516,7 @@ ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw, u64 time) * Prepare the external PHYs connected to this device for a timer sync * command. */ -int +static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) { @@ -5565,7 +5565,7 @@ ice_read_phy_tstamp_e830(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) * @tstamp_ready: contents of the Tx memory status register * */ -int +static int ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready) { u64 hi; @@ -5711,8 +5711,8 @@ void ice_ptp_init_phy_model(struct ice_hw *hw) * programming only a single port, instead use ice_ptp_one_port_cmd() to * ensure non-modified ports get properly initialized to ICE_PTP_NOP. */ -int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, - enum ice_ptp_tmr_cmd cmd, bool lock_sbq) +static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, + enum ice_ptp_tmr_cmd cmd, bool lock_sbq) { switch (hw->phy_model) { case ICE_PHY_ETH56G: diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 9ce77fbe4e..9357dfd327 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -195,12 +195,6 @@ int ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, enum ice_clk_src *clk_src); int -ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, - enum ice_ptp_tmr_cmd cmd, bool lock_sbq); -int -ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, - bool lock_sbq); -int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, enum ice_clk_src *clk_src); int @@ -213,16 +207,6 @@ ice_cfg_cgu_bypass_mux_e825c(struct ice_hw *hw, u8 port_num, bool clock_1588, unsigned int ena); int ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider); -/* E8 Family */ -int -ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, - bool lock_sbq); -int -ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, - bool lock_sbq); -int -ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready); - /** * ice_e822_time_ref - Get the current TIME_REF from capabilities * @hw: pointer to the HW structure -- 2.43.0