From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from jaguar.aricent.com (jaguar.aricent.com [125.19.57.27]) by dpdk.org (Postfix) with ESMTP id 1769B5A45 for ; Mon, 20 Apr 2015 16:37:59 +0200 (CEST) Received: from jaguar.aricent.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A1C7321A4FB for ; Mon, 20 Apr 2015 20:07:56 +0530 (IST) Received: from GURCASV01.AD.ARICENT.COM (unknown [10.203.26.90]) by jaguar.aricent.com (Postfix) with ESMTPS id 8923C21A4E5 for ; Mon, 20 Apr 2015 20:07:56 +0530 (IST) Received: from GURMBXV03.AD.ARICENT.COM (10.203.26.98) by GURMBXV03.AD.ARICENT.COM (10.203.26.98) with Microsoft SMTP Server (TLS) id 15.0.847.32; Mon, 20 Apr 2015 20:07:54 +0530 Received: from GURMBXV03.AD.ARICENT.COM ([169.254.5.48]) by GURMBXV03.AD.ARICENT.COM ([169.254.5.48]) with mapi id 15.00.0847.030; Mon, 20 Apr 2015 20:07:54 +0530 From: Ravi Kumar Iyer To: "dev@dpdk.org" Thread-Topic: cost of reading tsc register Thread-Index: AdB7d5VVdVB5RAEfSsem3X2LKd9jgg== Date: Mon, 20 Apr 2015 14:37:53 +0000 Message-ID: <115e8a38d223487488d22a99f53cc926@GURMBXV03.AD.ARICENT.COM> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.203.8.20] MIME-Version: 1.0 X-TM-AS-MML: disable Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: [dpdk-dev] cost of reading tsc register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Apr 2015 14:37:59 -0000 Hi, We were doing some code optimizations , running DPDK based applications, an= d chanced upon the rte_rdtsc function [ to read tsc timestamp register valu= e ] consuming cpu cycles of the order of 100clock cycles with a delta of up= to 40cycles at times [ 60-140 cycles] We are actually building up a cpu intensive application which is also very = clock cycle sensitive and this is impacting our implementation. To validate the same using a small/vanilla application we wrote a small cod= e and tested on a single core. Has anyone else faced a similar issue or are we doing something really atro= cious here. Below is the pseudo snip of the same: uint64_t g_tsc_cost[8] __rte_cache_aligned; void test_tsc_cost() { uint8_t i =3D 0; for (i =3D 0; i < 8 ; i++) { g_tsc_cost[i] =3D rte_rdtsc(); } } int main(int argc, char **argv) { int ret; unsigned lcore_id; ret =3D rte_eal_init(argc, argv); if (ret < 0) rte_panic("Cannot init EAL\n"); memset(g_tsc_cost,0,64); /* warm the cache */ uint64_t sc =3D rte_rdtsc(); /* start count */ test_tsc_cost(); uint64_t ec =3D rte_rdtsc(); /* end count */ printf("\n Total cost =3D %lu\n",(ec-sc)); uint8_t i =3D 0; for (i =3D 0; i < 8 ; i++) { printf("\n g_tsc_cost[%d]=3D%lu",i,g_tsc_cost[i]); /* here the values printed are 60-140 units apart */ } return 0; } Just to compare, On few bare metal implementations of non-intel processors,= we are seeing the similar code print values with a delta of 3-4 cycles and= thus its becoming a bit difficult to digest as well. Grateful for any hel= p/guidance here. Thanks ravi "DISCLAIMER: This message is proprietary to Aricent and is intended solely = for the use of the individual to whom it is addressed. It may contain privi= leged or confidential information and should not be circulated or used for = any purpose other than for what it is intended. If you have received this m= essage in error, please notify the originator immediately. If you are not t= he intended recipient, you are notified that you are strictly prohibited fr= om using, copying, altering, or disclosing the contents of this message. Ar= icent accepts no responsibility for loss or damage arising from the use of = the information transmitted by this email including damage from virus."