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Wed, 10 Apr 2019 02:15:24 +0000 From: Yongseok Koh To: "jerinjacobk@gmail.com" , Pavan Nikhilesh CC: Thomas Monjalon , dev , Jerin Jacob Thread-Topic: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU70NBBy90KINyHk2uyEO6wJhuRA== Date: Wed, 10 Apr 2019 02:15:24 +0000 Message-ID: <122A13B7-4883-4719-A682-AE3C40DDAA96@mellanox.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> <20190406142737.20091-2-jerinj@marvell.com> <54C87541-6DC7-4CAF-850B-8F7A4BF1C9BD@mellanox.com> In-Reply-To: <54C87541-6DC7-4CAF-850B-8F7A4BF1C9BD@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 538f5c71-2af2-442c-cdef-08d6bd5a6404 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: LQHNWVYdKr2I8UgbSBr5fhD2pX3NycZAGmtY2QBvjK1bAWbvqamNO6adYMnXbCYDt23rSHArHmJ0HRMNxN3q0hhJt0mYIRa+Z8Uv4xwds8VF49a+WRZGB2bb5dU7MwzFpl8LzTIoEAaC//d1obGCxkwl/S/lGDgLhvNFkbuhvYmnPIrIqX09QqUtDeWOsrxAfKSLjcUNO/gTz6KrYxkukQ3fz5FL0hzMivQywbooT+C2BKGwF8i9PjpoJ7BMaAqVMS37q9+jhXHDy5dOYUgGwDk/9YbqrUTBSOUzxarl6+tNIPgF0G3M5rThE/UWJ2AL0G3zIAL+qtfNQr9eQs7qBL9mv0IlJtBaX7RTp0KAyk81UkqxHCxPA5DJcvcSn91zuuWk8vSMV58StdxhUZGk6bf9t+CLrqAXVNpTWHjpUZ8= Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 538f5c71-2af2-442c-cdef-08d6bd5a6404 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2019 02:15:24.0675 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3948 Subject: Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Apr 2019 02:15:26 -0000 > On Apr 9, 2019, at 5:40 PM, Yongseok Koh wrote: >=20 >>=20 >> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote: >>=20 >> From: Pavan Nikhilesh >>=20 >> Currently, RTE_* flags are set based on the implementer ID but there mig= ht >> be some micro arch specific differences from the same vendor >> eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >>=20 >> Signed-off-by: Pavan Nikhilesh >> Signed-off-by: Jerin Jacob >> --- >> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- >> 1 file changed, 32 insertions(+), 5 deletions(-) >>=20 >> diff --git a/config/arm/meson.build b/config/arm/meson.build >> index 170a4981a..8de3f3e3a 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -52,12 +52,10 @@ flags_generic =3D [ >> ['RTE_USE_C11_MEM_MODEL', true], >> ['RTE_CACHE_LINE_SIZE', 128]] >> flags_cavium =3D [ >> - ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> ['RTE_MAX_NUMA_NODES', 2], >> ['RTE_MAX_LCORE', 96], >> - ['RTE_MAX_VFIO_GROUPS', 128], >> - ['RTE_USE_C11_MEM_MODEL', false]] >> + ['RTE_MAX_VFIO_GROUPS', 128]] >> flags_dpaa =3D [ >> ['RTE_MACHINE', '"dpaa"'], >> ['RTE_USE_C11_MEM_MODEL', true], >> @@ -71,6 +69,27 @@ flags_dpaa2 =3D [ >> ['RTE_MAX_NUMA_NODES', 1], >> ['RTE_MAX_LCORE', 16], >> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >> +flags_default_extra =3D [] >> +flags_thunderx_extra =3D [ >> + ['RTE_MACHINE', '"thunderx"'], >> + ['RTE_USE_C11_MEM_MODEL', false]] >> + >> +machine_args_generic =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['native', ['-march=3Dnative']], >> + ['0xd03', ['-mcpu=3Dcortex-a53']], >> + ['0xd04', ['-mcpu=3Dcortex-a35']], >> + ['0xd07', ['-mcpu=3Dcortex-a57']], >> + ['0xd08', ['-mcpu=3Dcortex-a72']], >> + ['0xd09', ['-mcpu=3Dcortex-a73']], >> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + >> +machine_args_cavium =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> + ['native', ['-march=3Dnative']], >> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > Looks like there's a mistake in rebasing it? > You should've removed machine_args_generic and machine_args_cavium > in the beginning of this file. >=20 > Other than that, it looks good to me. >=20 > BTW, thanks for the patch. I raised this issue before and I was supposed = to > make the change but you have taken it. >=20 > Yongseok >=20 >> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) >> impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] >> @@ -157,8 +176,16 @@ else >> endif >> foreach marg: machine[2] >> if marg[0] =3D=3D impl_pn >> - foreach f: marg[1] >> - machine_args +=3D f >> + foreach flag: marg[1] >> + if cc.has_argument(flag) >> + machine_args +=3D flag >> + endif >> + endforeach >> + # Apply any extra machine specific flags. >> + foreach flag: marg.get(2, flags_default_extra) >> + if flag.length() > 0 >> + dpdk_conf.set(flag[0], flag[1]) >> + endif And setting the extra flags doesn't work well with gcc < 7 because of the f= ollowing, # Primary part number based mcpu flags are supported # for gcc versions > 7 if cc.version().version_compare( '<7.0') or cmd_output.length() =3D=3D 0 if not meson.is_cross_build() and arm_force_native_march = =3D=3D true impl_pn =3D 'native' else impl_pn =3D 'default' endif endif Thanks, Yongseok >> endforeach >> endif >> endforeach >> --=20 >> 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id E0DA2A0096 for ; Wed, 10 Apr 2019 04:15:28 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6B8E4568A; Wed, 10 Apr 2019 04:15:27 +0200 (CEST) Received: from EUR02-VE1-obe.outbound.protection.outlook.com (mail-eopbgr20060.outbound.protection.outlook.com [40.107.2.60]) by dpdk.org (Postfix) with ESMTP id E73904F90 for ; Wed, 10 Apr 2019 04:15:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=L8Dk9pHLeod1AvLRHgUdLwryZOxkGAJOobojjnk8Ehw=; b=oFxlTm4/83AKLHciiK0UEKunVGfq1KoqFkwad8NNBWUQGJgU7GewDoCD1vayImb2saUqm5qrO5ziPua++DRlz0w3zhXoKdruDhrz5h4D1vE0lpJqIA019Yuviyf0OdPc/h+TeKr7kduOoWGqD+aTBtNg1IoR3cvRvoecdR4ktbI= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3948.eurprd05.prod.outlook.com (52.134.72.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1771.16; Wed, 10 Apr 2019 02:15:24 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Wed, 10 Apr 2019 02:15:24 +0000 From: Yongseok Koh To: "jerinjacobk@gmail.com" , Pavan Nikhilesh CC: Thomas Monjalon , dev , Jerin Jacob Thread-Topic: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU70NBBy90KINyHk2uyEO6wJhuRA== Date: Wed, 10 Apr 2019 02:15:24 +0000 Message-ID: <122A13B7-4883-4719-A682-AE3C40DDAA96@mellanox.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> <20190406142737.20091-2-jerinj@marvell.com> <54C87541-6DC7-4CAF-850B-8F7A4BF1C9BD@mellanox.com> In-Reply-To: <54C87541-6DC7-4CAF-850B-8F7A4BF1C9BD@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3948; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: LQHNWVYdKr2I8UgbSBr5fhD2pX3NycZAGmtY2QBvjK1bAWbvqamNO6adYMnXbCYDt23rSHArHmJ0HRMNxN3q0hhJt0mYIRa+Z8Uv4xwds8VF49a+WRZGB2bb5dU7MwzFpl8LzTIoEAaC//d1obGCxkwl/S/lGDgLhvNFkbuhvYmnPIrIqX09QqUtDeWOsrxAfKSLjcUNO/gTz6KrYxkukQ3fz5FL0hzMivQywbooT+C2BKGwF8i9PjpoJ7BMaAqVMS37q9+jhXHDy5dOYUgGwDk/9YbqrUTBSOUzxarl6+tNIPgF0G3M5rThE/UWJ2AL0G3zIAL+qtfNQr9eQs7qBL9mv0IlJtBaX7RTp0KAyk81UkqxHCxPA5DJcvcSn91zuuWk8vSMV58StdxhUZGk6bf9t+CLrqAXVNpTWHjpUZ8= Content-Type: text/plain; charset="UTF-8" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 538f5c71-2af2-442c-cdef-08d6bd5a6404 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2019 02:15:24.0675 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3948 Subject: Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190410021524.gfhPvD7od-OyprnmGKPNQUo5Oa2YdIVXeGUygEVIIVc@z> > On Apr 9, 2019, at 5:40 PM, Yongseok Koh wrote: >=20 >>=20 >> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote: >>=20 >> From: Pavan Nikhilesh >>=20 >> Currently, RTE_* flags are set based on the implementer ID but there mig= ht >> be some micro arch specific differences from the same vendor >> eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >>=20 >> Signed-off-by: Pavan Nikhilesh >> Signed-off-by: Jerin Jacob >> --- >> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- >> 1 file changed, 32 insertions(+), 5 deletions(-) >>=20 >> diff --git a/config/arm/meson.build b/config/arm/meson.build >> index 170a4981a..8de3f3e3a 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -52,12 +52,10 @@ flags_generic =3D [ >> ['RTE_USE_C11_MEM_MODEL', true], >> ['RTE_CACHE_LINE_SIZE', 128]] >> flags_cavium =3D [ >> - ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> ['RTE_MAX_NUMA_NODES', 2], >> ['RTE_MAX_LCORE', 96], >> - ['RTE_MAX_VFIO_GROUPS', 128], >> - ['RTE_USE_C11_MEM_MODEL', false]] >> + ['RTE_MAX_VFIO_GROUPS', 128]] >> flags_dpaa =3D [ >> ['RTE_MACHINE', '"dpaa"'], >> ['RTE_USE_C11_MEM_MODEL', true], >> @@ -71,6 +69,27 @@ flags_dpaa2 =3D [ >> ['RTE_MAX_NUMA_NODES', 1], >> ['RTE_MAX_LCORE', 16], >> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >> +flags_default_extra =3D [] >> +flags_thunderx_extra =3D [ >> + ['RTE_MACHINE', '"thunderx"'], >> + ['RTE_USE_C11_MEM_MODEL', false]] >> + >> +machine_args_generic =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['native', ['-march=3Dnative']], >> + ['0xd03', ['-mcpu=3Dcortex-a53']], >> + ['0xd04', ['-mcpu=3Dcortex-a35']], >> + ['0xd07', ['-mcpu=3Dcortex-a57']], >> + ['0xd08', ['-mcpu=3Dcortex-a72']], >> + ['0xd09', ['-mcpu=3Dcortex-a73']], >> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + >> +machine_args_cavium =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> + ['native', ['-march=3Dnative']], >> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > Looks like there's a mistake in rebasing it? > You should've removed machine_args_generic and machine_args_cavium > in the beginning of this file. >=20 > Other than that, it looks good to me. >=20 > BTW, thanks for the patch. I raised this issue before and I was supposed = to > make the change but you have taken it. >=20 > Yongseok >=20 >> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) >> impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] >> @@ -157,8 +176,16 @@ else >> endif >> foreach marg: machine[2] >> if marg[0] =3D=3D impl_pn >> - foreach f: marg[1] >> - machine_args +=3D f >> + foreach flag: marg[1] >> + if cc.has_argument(flag) >> + machine_args +=3D flag >> + endif >> + endforeach >> + # Apply any extra machine specific flags. >> + foreach flag: marg.get(2, flags_default_extra) >> + if flag.length() > 0 >> + dpdk_conf.set(flag[0], flag[1]) >> + endif And setting the extra flags doesn't work well with gcc < 7 because of the f= ollowing, # Primary part number based mcpu flags are supported # for gcc versions > 7 if cc.version().version_compare( '<7.0') or cmd_output.length() =3D=3D 0 if not meson.is_cross_build() and arm_force_native_march = =3D=3D true impl_pn =3D 'native' else impl_pn =3D 'default' endif endif Thanks, Yongseok >> endforeach >> endif >> endforeach >> --=20 >> 2.21.0